1 /* 2 * Copyright 2004, 2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #define CONFIG_PCI /* enable any pci type devices */ 40 #define CONFIG_PCI1 /* PCI controller 1 */ 41 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 42 #undef CONFIG_RIO 43 #undef CONFIG_PCI2 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 46 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 47 #define CONFIG_ENV_OVERWRITE 48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 49 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 50 #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 51 52 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 54 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 55 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 56 57 58 /* 59 * When initializing flash, if we cannot find the manufacturer ID, 60 * assume this is the AMD flash associated with the CDS board. 61 * This allows booting from a promjet. 62 */ 63 #define CONFIG_ASSUME_AMD_FLASH 64 65 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 66 67 #ifndef __ASSEMBLY__ 68 extern unsigned long get_clock_freq(void); 69 #endif 70 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 71 72 /* 73 * These can be toggled for performance analysis, otherwise use default. 74 */ 75 #define CONFIG_L2_CACHE /* toggle L2 cache */ 76 #define CONFIG_BTB /* toggle branch predition */ 77 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 78 #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ 79 80 /* 81 * Only possible on E500 Version 2 or newer cores. 82 */ 83 #define CONFIG_ENABLE_36BIT_PHYS 1 84 85 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 86 87 #undef CFG_DRAM_TEST /* memory test, takes time */ 88 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 89 #define CFG_MEMTEST_END 0x00400000 90 91 /* 92 * Base addresses -- Note these are effective addresses where the 93 * actual resources get mapped (not physical addresses) 94 */ 95 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 96 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 97 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 98 99 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 100 #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) 101 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 102 103 /* 104 * DDR Setup 105 */ 106 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 107 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 108 109 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 110 111 /* 112 * Make sure required options are set 113 */ 114 #ifndef CONFIG_SPD_EEPROM 115 #error ("CONFIG_SPD_EEPROM is required") 116 #endif 117 118 #undef CONFIG_CLOCKS_IN_MHZ 119 120 /* 121 * Local Bus Definitions 122 */ 123 124 /* 125 * FLASH on the Local Bus 126 * Two banks, 8M each, using the CFI driver. 127 * Boot from BR0/OR0 bank at 0xff00_0000 128 * Alternate BR1/OR1 bank at 0xff80_0000 129 * 130 * BR0, BR1: 131 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 132 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 133 * Port Size = 16 bits = BRx[19:20] = 10 134 * Use GPCM = BRx[24:26] = 000 135 * Valid = BRx[31] = 1 136 * 137 * 0 4 8 12 16 20 24 28 138 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 139 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 140 * 141 * OR0, OR1: 142 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 143 * Reserved ORx[17:18] = 11, confusion here? 144 * CSNT = ORx[20] = 1 145 * ACS = half cycle delay = ORx[21:22] = 11 146 * SCY = 6 = ORx[24:27] = 0110 147 * TRLX = use relaxed timing = ORx[29] = 1 148 * EAD = use external address latch delay = OR[31] = 1 149 * 150 * 0 4 8 12 16 20 24 28 151 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 152 */ 153 154 #define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */ 155 #define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ 156 157 #define CFG_BR0_PRELIM 0xff801001 158 #define CFG_BR1_PRELIM 0xff001001 159 160 #define CFG_OR0_PRELIM 0xff806e65 161 #define CFG_OR1_PRELIM 0xff806e65 162 163 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} 164 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 165 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 166 #undef CFG_FLASH_CHECKSUM 167 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 168 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 169 170 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 171 172 #define CFG_FLASH_CFI_DRIVER 173 #define CFG_FLASH_CFI 174 #define CFG_FLASH_EMPTY_INFO 175 176 177 /* 178 * SDRAM on the Local Bus 179 */ 180 #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 181 #define CFG_LBC_CACHE_SIZE 64 182 #define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ 183 #define CFG_LBC_NONCACHE_SIZE 64 184 185 #define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */ 186 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 187 188 /* 189 * Base Register 2 and Option Register 2 configure SDRAM. 190 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 191 * 192 * For BR2, need: 193 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 194 * port-size = 32-bits = BR2[19:20] = 11 195 * no parity checking = BR2[21:22] = 00 196 * SDRAM for MSEL = BR2[24:26] = 011 197 * Valid = BR[31] = 1 198 * 199 * 0 4 8 12 16 20 24 28 200 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 201 * 202 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 203 * FIXME: the top 17 bits of BR2. 204 */ 205 206 #define CFG_BR2_PRELIM 0xf0001861 207 208 /* 209 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 210 * 211 * For OR2, need: 212 * 64MB mask for AM, OR2[0:7] = 1111 1100 213 * XAM, OR2[17:18] = 11 214 * 9 columns OR2[19-21] = 010 215 * 13 rows OR2[23-25] = 100 216 * EAD set for extra time OR[31] = 1 217 * 218 * 0 4 8 12 16 20 24 28 219 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 220 */ 221 222 #define CFG_OR2_PRELIM 0xfc006901 223 224 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 225 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 226 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 227 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 228 229 /* 230 * LSDMR masks 231 */ 232 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 233 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 234 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 235 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 236 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 237 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 238 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 239 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 240 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 241 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 242 243 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 244 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 245 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 246 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 247 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 248 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 249 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 250 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 251 252 /* 253 * Common settings for all Local Bus SDRAM commands. 254 * At run time, either BSMA1516 (for CPU 1.1) 255 * or BSMA1617 (for CPU 1.0) (old) 256 * is OR'ed in too. 257 */ 258 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 259 | CFG_LBC_LSDMR_PRETOACT7 \ 260 | CFG_LBC_LSDMR_ACTTORW7 \ 261 | CFG_LBC_LSDMR_BL8 \ 262 | CFG_LBC_LSDMR_WRC4 \ 263 | CFG_LBC_LSDMR_CL3 \ 264 | CFG_LBC_LSDMR_RFEN \ 265 ) 266 267 /* 268 * The CADMUS registers are connected to CS3 on CDS. 269 * The new memory map places CADMUS at 0xf8000000. 270 * 271 * For BR3, need: 272 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 273 * port-size = 8-bits = BR[19:20] = 01 274 * no parity checking = BR[21:22] = 00 275 * GPMC for MSEL = BR[24:26] = 000 276 * Valid = BR[31] = 1 277 * 278 * 0 4 8 12 16 20 24 28 279 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 280 * 281 * For OR3, need: 282 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 283 * disable buffer ctrl OR[19] = 0 284 * CSNT OR[20] = 1 285 * ACS OR[21:22] = 11 286 * XACS OR[23] = 1 287 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 288 * SETA OR[28] = 0 289 * TRLX OR[29] = 1 290 * EHTR OR[30] = 1 291 * EAD extra time OR[31] = 1 292 * 293 * 0 4 8 12 16 20 24 28 294 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 295 */ 296 297 #define CADMUS_BASE_ADDR 0xf8000000 298 #define CFG_BR3_PRELIM 0xf8000801 299 #define CFG_OR3_PRELIM 0xfff00ff7 300 301 #define CONFIG_L1_INIT_RAM 302 #define CFG_INIT_RAM_LOCK 1 303 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 304 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 305 306 #define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 307 308 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 309 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 310 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 311 312 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 313 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 314 315 /* Serial Port */ 316 #define CONFIG_CONS_INDEX 2 317 #undef CONFIG_SERIAL_SOFTWARE_FIFO 318 #define CFG_NS16550 319 #define CFG_NS16550_SERIAL 320 #define CFG_NS16550_REG_SIZE 1 321 #define CFG_NS16550_CLK get_bus_freq(0) 322 323 #define CFG_BAUDRATE_TABLE \ 324 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 325 326 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 327 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 328 329 /* Use the HUSH parser */ 330 #define CFG_HUSH_PARSER 331 #ifdef CFG_HUSH_PARSER 332 #define CFG_PROMPT_HUSH_PS2 "> " 333 #endif 334 335 /* pass open firmware flat tree */ 336 #define CONFIG_OF_FLAT_TREE 1 337 #define CONFIG_OF_BOARD_SETUP 1 338 339 #define OF_CPU "PowerPC,8548@0" 340 #define OF_SOC "soc8548@e0000000" 341 #define OF_TBCLK (bd->bi_busfreq / 8) 342 #define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" 343 #define OF_PCI "pci@e0008000" 344 345 /* 346 * I2C 347 */ 348 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 349 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 350 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 351 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 352 #define CFG_I2C_EEPROM_ADDR 0x57 353 #define CFG_I2C_SLAVE 0x7F 354 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 355 #define CFG_I2C_OFFSET 0x3000 356 357 /* 358 * General PCI 359 * Memory space is mapped 1-1, but I/O space must start from 0. 360 */ 361 #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 362 363 #define CFG_PCI1_MEM_BASE 0x80000000 364 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 365 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 366 #define CFG_PCI1_IO_BASE 0x00000000 367 #define CFG_PCI1_IO_PHYS 0xe2000000 368 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 369 370 #ifdef CONFIG_PCI2 371 #define CFG_PCI2_MEM_BASE 0xa0000000 372 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 373 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 374 #define CFG_PCI2_IO_BASE 0x00000000 375 #define CFG_PCI2_IO_PHYS 0xe2800000 376 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 377 #endif 378 379 #ifdef CONFIG_PCIE1 380 #define CFG_PCIE1_MEM_BASE 0xa0000000 381 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 382 #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 383 #define CFG_PCIE1_IO_BASE 0x00000000 384 #define CFG_PCIE1_IO_PHYS 0xe3000000 385 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ 386 #endif 387 388 #ifdef CONFIG_RIO 389 /* 390 * RapidIO MMU 391 */ 392 #define CFG_RIO_MEM_BASE 0xC0000000 393 #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ 394 #endif 395 396 #ifdef CONFIG_LEGACY 397 #define BRIDGE_ID 17 398 #define VIA_ID 2 399 #else 400 #define BRIDGE_ID 28 401 #define VIA_ID 4 402 #endif 403 404 #if defined(CONFIG_PCI) 405 406 #define CONFIG_NET_MULTI 407 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 408 409 #undef CONFIG_EEPRO100 410 #undef CONFIG_TULIP 411 412 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 413 414 /* PCI view of System Memory */ 415 #define CFG_PCI_MEMORY_BUS 0x00000000 416 #define CFG_PCI_MEMORY_PHYS 0x00000000 417 #define CFG_PCI_MEMORY_SIZE 0x80000000 418 419 #endif /* CONFIG_PCI */ 420 421 422 #if defined(CONFIG_TSEC_ENET) 423 424 #ifndef CONFIG_NET_MULTI 425 #define CONFIG_NET_MULTI 1 426 #endif 427 428 #define CONFIG_MII 1 /* MII PHY management */ 429 #define CONFIG_TSEC1 1 430 #define CONFIG_TSEC1_NAME "eTSEC0" 431 #define CONFIG_TSEC2 1 432 #define CONFIG_TSEC2_NAME "eTSEC1" 433 #define CONFIG_TSEC3 1 434 #define CONFIG_TSEC3_NAME "eTSEC2" 435 #define CONFIG_TSEC4 436 #define CONFIG_TSEC4_NAME "eTSEC3" 437 #undef CONFIG_MPC85XX_FEC 438 439 #define TSEC1_PHY_ADDR 0 440 #define TSEC2_PHY_ADDR 1 441 #define TSEC3_PHY_ADDR 2 442 #define TSEC4_PHY_ADDR 3 443 444 #define TSEC1_PHYIDX 0 445 #define TSEC2_PHYIDX 0 446 #define TSEC3_PHYIDX 0 447 #define TSEC4_PHYIDX 0 448 #define TSEC1_FLAGS TSEC_GIGABIT 449 #define TSEC2_FLAGS TSEC_GIGABIT 450 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 451 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 452 453 /* Options are: eTSEC[0-3] */ 454 #define CONFIG_ETHPRIME "eTSEC0" 455 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 456 #endif /* CONFIG_TSEC_ENET */ 457 458 /* 459 * Environment 460 */ 461 #define CFG_ENV_IS_IN_FLASH 1 462 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 463 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 464 #define CFG_ENV_SIZE 0x2000 465 466 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 467 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 468 469 /* 470 * BOOTP options 471 */ 472 #define CONFIG_BOOTP_BOOTFILESIZE 473 #define CONFIG_BOOTP_BOOTPATH 474 #define CONFIG_BOOTP_GATEWAY 475 #define CONFIG_BOOTP_HOSTNAME 476 477 478 /* 479 * Command line configuration. 480 */ 481 #include <config_cmd_default.h> 482 483 #define CONFIG_CMD_PING 484 #define CONFIG_CMD_I2C 485 #define CONFIG_CMD_MII 486 487 #if defined(CONFIG_PCI) 488 #define CONFIG_CMD_PCI 489 #endif 490 491 492 #undef CONFIG_WATCHDOG /* watchdog disabled */ 493 494 /* 495 * Miscellaneous configurable options 496 */ 497 #define CFG_LONGHELP /* undef to save memory */ 498 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 499 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 500 #if defined(CONFIG_CMD_KGDB) 501 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 502 #else 503 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 504 #endif 505 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 506 #define CFG_MAXARGS 16 /* max number of command args */ 507 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 508 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 509 510 /* 511 * For booting Linux, the board info and command line data 512 * have to be in the first 8 MB of memory, since this is 513 * the maximum mapped by the Linux kernel during initialization. 514 */ 515 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 516 517 /* Cache Configuration */ 518 #define CFG_DCACHE_SIZE 32768 519 #define CFG_CACHELINE_SIZE 32 520 #if defined(CONFIG_CMD_KGDB) 521 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 522 #endif 523 524 /* 525 * Internal Definitions 526 * 527 * Boot Flags 528 */ 529 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 530 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 531 532 #if defined(CONFIG_CMD_KGDB) 533 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 534 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 535 #endif 536 537 /* 538 * Environment Configuration 539 */ 540 541 /* The mac addresses for all ethernet interface */ 542 #if defined(CONFIG_TSEC_ENET) 543 #define CONFIG_HAS_ETH0 544 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 545 #define CONFIG_HAS_ETH1 546 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 547 #define CONFIG_HAS_ETH2 548 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 549 #define CONFIG_HAS_ETH3 550 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 551 #endif 552 553 #define CONFIG_IPADDR 192.168.1.253 554 555 #define CONFIG_HOSTNAME unknown 556 #define CONFIG_ROOTPATH /nfsroot 557 #define CONFIG_BOOTFILE 8548cds/uImage.uboot 558 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 559 560 #define CONFIG_SERVERIP 192.168.1.1 561 #define CONFIG_GATEWAYIP 192.168.1.1 562 #define CONFIG_NETMASK 255.255.255.0 563 564 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 565 566 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 567 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 568 569 #define CONFIG_BAUDRATE 115200 570 571 #if defined(CONFIG_PCIE1) 572 #define PCIE_ENV \ 573 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 574 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 575 "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 576 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 577 "pci d $b.0 130 1\0" \ 578 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \ 579 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\ 580 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 581 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 582 "pcie1regs=setenv a e000a; run pciereg\0" \ 583 "pcie1cfg=setenv b 3; run pciecfg\0" \ 584 "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ 585 "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" 586 #else 587 #define PCIE_ENV "" 588 #endif 589 590 #if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) 591 #define PCI_ENV \ 592 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 593 "echo e;md ${a}e00 9\0" \ 594 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \ 595 "pci d.w $b.0 56 1\0" \ 596 "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ 597 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" 598 #else 599 #define PCI_ENV "" 600 #endif 601 602 #if defined(CONFIG_PCI1) 603 #define PCI_ENV1 \ 604 "pci1regs=setenv a e0008; run pcireg\0" \ 605 "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \ 606 "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0" 607 #else 608 #define PCI_ENV1 "" 609 #endif 610 611 #if defined(CONFIG_PCI2) 612 #define PCI_ENV2 \ 613 "pci2regs=setenv a e0009; run pcireg\0" \ 614 "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \ 615 "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0" 616 #else 617 #define PCI_ENV2 "" 618 #endif 619 620 #if defined(CONFIG_TSEC_ENET) 621 #define ENET_ENV \ 622 "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ 623 "md ${a}098 2\0" \ 624 "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ 625 "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ 626 "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ 627 "echo mib;md ${a}680 31\0" \ 628 "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ 629 "enet1regs=setenv a e0024; run enetreg\0" \ 630 "enet2regs=setenv a e0025; run enetreg\0" \ 631 "enet3regs=setenv a e0026; run enetreg\0" \ 632 "enet4regs=setenv a e0027; run enetreg\0" 633 #else 634 #define ENET_ENV "" 635 #endif 636 637 #define CONFIG_EXTRA_ENV_SETTINGS \ 638 "netdev=eth0\0" \ 639 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 640 "tftpflash=tftpboot $loadaddr $uboot; " \ 641 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 642 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 643 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 644 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 645 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 646 "consoledev=ttyS1\0" \ 647 "ramdiskaddr=2000000\0" \ 648 "ramdiskfile=ramdisk.uboot\0" \ 649 "fdtaddr=c00000\0" \ 650 "fdtfile=mpc8548cds.dtb\0" \ 651 "eoi=mw e00400b0 0\0" \ 652 "iack=md e00400a0 1\0" \ 653 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ 654 "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ 655 "ddrregs=setenv a e0002; run ddrreg\0" \ 656 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ 657 "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ 658 "guregs=setenv a e00e0; run gureg\0" \ 659 "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ 660 "ecmregs=setenv a e0001; run ecmreg\0" \ 661 "lawregs=md e0000c08 4b\0" \ 662 "lbcregs=md e0005000 36\0" \ 663 "dma0regs=md e0021100 12\0" \ 664 "dma1regs=md e0021180 12\0" \ 665 "dma2regs=md e0021200 12\0" \ 666 "dma3regs=md e0021280 12\0" \ 667 PCIE_ENV \ 668 PCI_ENV \ 669 PCI_ENV1 \ 670 PCI_ENV2 \ 671 ENET_ENV 672 673 #define CONFIG_NFSBOOTCOMMAND \ 674 "setenv bootargs root=/dev/nfs rw " \ 675 "nfsroot=$serverip:$rootpath " \ 676 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 677 "console=$consoledev,$baudrate $othbootargs;" \ 678 "tftp $loadaddr $bootfile;" \ 679 "tftp $fdtaddr $fdtfile;" \ 680 "bootm $loadaddr - $fdtaddr" 681 682 683 #define CONFIG_RAMBOOTCOMMAND \ 684 "setenv bootargs root=/dev/ram rw " \ 685 "console=$consoledev,$baudrate $othbootargs;" \ 686 "tftp $ramdiskaddr $ramdiskfile;" \ 687 "tftp $loadaddr $bootfile;" \ 688 "tftp $fdtaddr $fdtfile;" \ 689 "bootm $loadaddr $ramdiskaddr $fdtaddr" 690 691 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 692 693 #endif /* __CONFIG_H */ 694