1 /* 2 * Copyright 2004, 2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #ifndef CONFIG_SYS_TEXT_BASE 40 #define CONFIG_SYS_TEXT_BASE 0xfff80000 41 #endif 42 43 #define CONFIG_PCI /* enable any pci type devices */ 44 #define CONFIG_PCI1 /* PCI controller 1 */ 45 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 46 #undef CONFIG_RIO 47 #undef CONFIG_PCI2 48 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 49 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 50 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 51 52 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 53 #define CONFIG_ENV_OVERWRITE 54 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 55 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 56 57 #define CONFIG_FSL_VIA 58 59 #ifndef __ASSEMBLY__ 60 extern unsigned long get_clock_freq(void); 61 #endif 62 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 63 64 /* 65 * These can be toggled for performance analysis, otherwise use default. 66 */ 67 #define CONFIG_L2_CACHE /* toggle L2 cache */ 68 #define CONFIG_BTB /* toggle branch predition */ 69 70 /* 71 * Only possible on E500 Version 2 or newer cores. 72 */ 73 #define CONFIG_ENABLE_36BIT_PHYS 1 74 75 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 76 #define CONFIG_SYS_MEMTEST_END 0x00400000 77 78 /* 79 * Base addresses -- Note these are effective addresses where the 80 * actual resources get mapped (not physical addresses) 81 */ 82 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 83 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 84 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 85 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 86 87 /* DDR Setup */ 88 #define CONFIG_FSL_DDR2 89 #undef CONFIG_FSL_DDR_INTERACTIVE 90 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 91 #define CONFIG_DDR_SPD 92 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 93 94 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 95 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 96 97 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 98 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 99 100 #define CONFIG_NUM_DDR_CONTROLLERS 1 101 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 102 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 103 104 /* I2C addresses of SPD EEPROMs */ 105 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 106 107 /* Make sure required options are set */ 108 #ifndef CONFIG_SPD_EEPROM 109 #error ("CONFIG_SPD_EEPROM is required") 110 #endif 111 112 #undef CONFIG_CLOCKS_IN_MHZ 113 114 /* 115 * Local Bus Definitions 116 */ 117 118 /* 119 * FLASH on the Local Bus 120 * Two banks, 8M each, using the CFI driver. 121 * Boot from BR0/OR0 bank at 0xff00_0000 122 * Alternate BR1/OR1 bank at 0xff80_0000 123 * 124 * BR0, BR1: 125 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 126 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 127 * Port Size = 16 bits = BRx[19:20] = 10 128 * Use GPCM = BRx[24:26] = 000 129 * Valid = BRx[31] = 1 130 * 131 * 0 4 8 12 16 20 24 28 132 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 133 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 134 * 135 * OR0, OR1: 136 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 137 * Reserved ORx[17:18] = 11, confusion here? 138 * CSNT = ORx[20] = 1 139 * ACS = half cycle delay = ORx[21:22] = 11 140 * SCY = 6 = ORx[24:27] = 0110 141 * TRLX = use relaxed timing = ORx[29] = 1 142 * EAD = use external address latch delay = OR[31] = 1 143 * 144 * 0 4 8 12 16 20 24 28 145 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 146 */ 147 148 #define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ 149 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 150 151 #define CONFIG_SYS_BR0_PRELIM 0xff801001 152 #define CONFIG_SYS_BR1_PRELIM 0xff001001 153 154 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 155 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 156 157 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 158 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 159 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 160 #undef CONFIG_SYS_FLASH_CHECKSUM 161 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 162 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 163 164 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 165 166 #define CONFIG_FLASH_CFI_DRIVER 167 #define CONFIG_SYS_FLASH_CFI 168 #define CONFIG_SYS_FLASH_EMPTY_INFO 169 170 171 /* 172 * SDRAM on the Local Bus 173 */ 174 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 175 #define CONFIG_SYS_LBC_CACHE_SIZE 64 176 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ 177 #define CONFIG_SYS_LBC_NONCACHE_SIZE 64 178 179 #define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ 180 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 181 182 /* 183 * Base Register 2 and Option Register 2 configure SDRAM. 184 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 185 * 186 * For BR2, need: 187 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 188 * port-size = 32-bits = BR2[19:20] = 11 189 * no parity checking = BR2[21:22] = 00 190 * SDRAM for MSEL = BR2[24:26] = 011 191 * Valid = BR[31] = 1 192 * 193 * 0 4 8 12 16 20 24 28 194 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 195 * 196 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 197 * FIXME: the top 17 bits of BR2. 198 */ 199 200 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 201 202 /* 203 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 204 * 205 * For OR2, need: 206 * 64MB mask for AM, OR2[0:7] = 1111 1100 207 * XAM, OR2[17:18] = 11 208 * 9 columns OR2[19-21] = 010 209 * 13 rows OR2[23-25] = 100 210 * EAD set for extra time OR[31] = 1 211 * 212 * 0 4 8 12 16 20 24 28 213 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 214 */ 215 216 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 217 218 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 219 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 220 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 221 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 222 223 /* 224 * Common settings for all Local Bus SDRAM commands. 225 * At run time, either BSMA1516 (for CPU 1.1) 226 * or BSMA1617 (for CPU 1.0) (old) 227 * is OR'ed in too. 228 */ 229 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 230 | LSDMR_PRETOACT7 \ 231 | LSDMR_ACTTORW7 \ 232 | LSDMR_BL8 \ 233 | LSDMR_WRC4 \ 234 | LSDMR_CL3 \ 235 | LSDMR_RFEN \ 236 ) 237 238 /* 239 * The CADMUS registers are connected to CS3 on CDS. 240 * The new memory map places CADMUS at 0xf8000000. 241 * 242 * For BR3, need: 243 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 244 * port-size = 8-bits = BR[19:20] = 01 245 * no parity checking = BR[21:22] = 00 246 * GPMC for MSEL = BR[24:26] = 000 247 * Valid = BR[31] = 1 248 * 249 * 0 4 8 12 16 20 24 28 250 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 251 * 252 * For OR3, need: 253 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 254 * disable buffer ctrl OR[19] = 0 255 * CSNT OR[20] = 1 256 * ACS OR[21:22] = 11 257 * XACS OR[23] = 1 258 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 259 * SETA OR[28] = 0 260 * TRLX OR[29] = 1 261 * EHTR OR[30] = 1 262 * EAD extra time OR[31] = 1 263 * 264 * 0 4 8 12 16 20 24 28 265 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 266 */ 267 268 #define CONFIG_FSL_CADMUS 269 270 #define CADMUS_BASE_ADDR 0xf8000000 271 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 272 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 273 274 #define CONFIG_SYS_INIT_RAM_LOCK 1 275 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 276 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 277 278 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 279 280 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 281 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 282 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 283 284 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 285 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 286 287 /* Serial Port */ 288 #define CONFIG_CONS_INDEX 2 289 #define CONFIG_SYS_NS16550 290 #define CONFIG_SYS_NS16550_SERIAL 291 #define CONFIG_SYS_NS16550_REG_SIZE 1 292 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 293 294 #define CONFIG_SYS_BAUDRATE_TABLE \ 295 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 296 297 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 298 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 299 300 /* Use the HUSH parser */ 301 #define CONFIG_SYS_HUSH_PARSER 302 #ifdef CONFIG_SYS_HUSH_PARSER 303 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 304 #endif 305 306 /* pass open firmware flat tree */ 307 #define CONFIG_OF_LIBFDT 1 308 #define CONFIG_OF_BOARD_SETUP 1 309 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 310 311 /* 312 * I2C 313 */ 314 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 315 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 316 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 317 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 318 #define CONFIG_SYS_I2C_SLAVE 0x7F 319 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 320 #define CONFIG_SYS_I2C_OFFSET 0x3000 321 322 /* EEPROM */ 323 #define CONFIG_ID_EEPROM 324 #define CONFIG_SYS_I2C_EEPROM_CCID 325 #define CONFIG_SYS_ID_EEPROM 326 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 327 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 328 329 /* 330 * General PCI 331 * Memory space is mapped 1-1, but I/O space must start from 0. 332 */ 333 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 334 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 335 336 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 337 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 338 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 339 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 340 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 341 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 342 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 343 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 344 345 #ifdef CONFIG_PCI2 346 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 347 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 348 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 349 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 350 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 351 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 352 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 353 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 354 #endif 355 356 #ifdef CONFIG_PCIE1 357 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 358 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 359 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 360 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 361 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 362 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 363 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 364 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 365 #endif 366 367 #ifdef CONFIG_RIO 368 /* 369 * RapidIO MMU 370 */ 371 #define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 372 #define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 373 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 374 #endif 375 376 #ifdef CONFIG_LEGACY 377 #define BRIDGE_ID 17 378 #define VIA_ID 2 379 #else 380 #define BRIDGE_ID 28 381 #define VIA_ID 4 382 #endif 383 384 #if defined(CONFIG_PCI) 385 386 #define CONFIG_NET_MULTI 387 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 388 389 #undef CONFIG_EEPRO100 390 #undef CONFIG_TULIP 391 392 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 393 394 #endif /* CONFIG_PCI */ 395 396 397 #if defined(CONFIG_TSEC_ENET) 398 399 #ifndef CONFIG_NET_MULTI 400 #define CONFIG_NET_MULTI 1 401 #endif 402 403 #define CONFIG_MII 1 /* MII PHY management */ 404 #define CONFIG_TSEC1 1 405 #define CONFIG_TSEC1_NAME "eTSEC0" 406 #define CONFIG_TSEC2 1 407 #define CONFIG_TSEC2_NAME "eTSEC1" 408 #define CONFIG_TSEC3 1 409 #define CONFIG_TSEC3_NAME "eTSEC2" 410 #define CONFIG_TSEC4 411 #define CONFIG_TSEC4_NAME "eTSEC3" 412 #undef CONFIG_MPC85XX_FEC 413 414 #define TSEC1_PHY_ADDR 0 415 #define TSEC2_PHY_ADDR 1 416 #define TSEC3_PHY_ADDR 2 417 #define TSEC4_PHY_ADDR 3 418 419 #define TSEC1_PHYIDX 0 420 #define TSEC2_PHYIDX 0 421 #define TSEC3_PHYIDX 0 422 #define TSEC4_PHYIDX 0 423 #define TSEC1_FLAGS TSEC_GIGABIT 424 #define TSEC2_FLAGS TSEC_GIGABIT 425 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 426 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 427 428 /* Options are: eTSEC[0-3] */ 429 #define CONFIG_ETHPRIME "eTSEC0" 430 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 431 #endif /* CONFIG_TSEC_ENET */ 432 433 /* 434 * Environment 435 */ 436 #define CONFIG_ENV_IS_IN_FLASH 1 437 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 438 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 439 #define CONFIG_ENV_SIZE 0x2000 440 441 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 442 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 443 444 /* 445 * BOOTP options 446 */ 447 #define CONFIG_BOOTP_BOOTFILESIZE 448 #define CONFIG_BOOTP_BOOTPATH 449 #define CONFIG_BOOTP_GATEWAY 450 #define CONFIG_BOOTP_HOSTNAME 451 452 453 /* 454 * Command line configuration. 455 */ 456 #include <config_cmd_default.h> 457 458 #define CONFIG_CMD_PING 459 #define CONFIG_CMD_I2C 460 #define CONFIG_CMD_MII 461 #define CONFIG_CMD_ELF 462 #define CONFIG_CMD_IRQ 463 #define CONFIG_CMD_SETEXPR 464 #define CONFIG_CMD_REGINFO 465 466 #if defined(CONFIG_PCI) 467 #define CONFIG_CMD_PCI 468 #endif 469 470 471 #undef CONFIG_WATCHDOG /* watchdog disabled */ 472 473 /* 474 * Miscellaneous configurable options 475 */ 476 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 477 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 478 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 479 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 480 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 481 #if defined(CONFIG_CMD_KGDB) 482 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 483 #else 484 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 485 #endif 486 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 487 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 488 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 489 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 490 491 /* 492 * For booting Linux, the board info and command line data 493 * have to be in the first 16 MB of memory, since this is 494 * the maximum mapped by the Linux kernel during initialization. 495 */ 496 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 497 498 #if defined(CONFIG_CMD_KGDB) 499 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 500 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 501 #endif 502 503 /* 504 * Environment Configuration 505 */ 506 507 /* The mac addresses for all ethernet interface */ 508 #if defined(CONFIG_TSEC_ENET) 509 #define CONFIG_HAS_ETH0 510 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 511 #define CONFIG_HAS_ETH1 512 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 513 #define CONFIG_HAS_ETH2 514 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 515 #define CONFIG_HAS_ETH3 516 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 517 #endif 518 519 #define CONFIG_IPADDR 192.168.1.253 520 521 #define CONFIG_HOSTNAME unknown 522 #define CONFIG_ROOTPATH /nfsroot 523 #define CONFIG_BOOTFILE 8548cds/uImage.uboot 524 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 525 526 #define CONFIG_SERVERIP 192.168.1.1 527 #define CONFIG_GATEWAYIP 192.168.1.1 528 #define CONFIG_NETMASK 255.255.255.0 529 530 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 531 532 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 533 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 534 535 #define CONFIG_BAUDRATE 115200 536 537 #define CONFIG_EXTRA_ENV_SETTINGS \ 538 "netdev=eth0\0" \ 539 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 540 "tftpflash=tftpboot $loadaddr $uboot; " \ 541 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 542 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 543 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 544 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 545 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 546 "consoledev=ttyS1\0" \ 547 "ramdiskaddr=2000000\0" \ 548 "ramdiskfile=ramdisk.uboot\0" \ 549 "fdtaddr=c00000\0" \ 550 "fdtfile=mpc8548cds.dtb\0" 551 552 #define CONFIG_NFSBOOTCOMMAND \ 553 "setenv bootargs root=/dev/nfs rw " \ 554 "nfsroot=$serverip:$rootpath " \ 555 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 556 "console=$consoledev,$baudrate $othbootargs;" \ 557 "tftp $loadaddr $bootfile;" \ 558 "tftp $fdtaddr $fdtfile;" \ 559 "bootm $loadaddr - $fdtaddr" 560 561 562 #define CONFIG_RAMBOOTCOMMAND \ 563 "setenv bootargs root=/dev/ram rw " \ 564 "console=$consoledev,$baudrate $othbootargs;" \ 565 "tftp $ramdiskaddr $ramdiskfile;" \ 566 "tftp $loadaddr $bootfile;" \ 567 "tftp $fdtaddr $fdtfile;" \ 568 "bootm $loadaddr $ramdiskaddr $fdtaddr" 569 570 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 571 572 #endif /* __CONFIG_H */ 573