1 /* 2 * Copyright 2004, 2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #define CONFIG_PCI /* enable any pci type devices */ 40 #define CONFIG_PCI1 /* PCI controller 1 */ 41 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 42 #undef CONFIG_RIO 43 #undef CONFIG_PCI2 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 46 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 47 48 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 49 #define CONFIG_ENV_OVERWRITE 50 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 52 53 #define CONFIG_FSL_VIA 54 55 #ifndef __ASSEMBLY__ 56 extern unsigned long get_clock_freq(void); 57 #endif 58 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 59 60 /* 61 * These can be toggled for performance analysis, otherwise use default. 62 */ 63 #define CONFIG_L2_CACHE /* toggle L2 cache */ 64 #define CONFIG_BTB /* toggle branch predition */ 65 66 /* 67 * Only possible on E500 Version 2 or newer cores. 68 */ 69 #define CONFIG_ENABLE_36BIT_PHYS 1 70 71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 72 #define CONFIG_SYS_MEMTEST_END 0x00400000 73 74 /* 75 * Base addresses -- Note these are effective addresses where the 76 * actual resources get mapped (not physical addresses) 77 */ 78 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 79 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 80 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 81 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 82 83 /* DDR Setup */ 84 #define CONFIG_FSL_DDR2 85 #undef CONFIG_FSL_DDR_INTERACTIVE 86 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 87 #define CONFIG_DDR_SPD 88 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 89 90 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 91 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 92 93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 95 96 #define CONFIG_NUM_DDR_CONTROLLERS 1 97 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 98 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 99 100 /* I2C addresses of SPD EEPROMs */ 101 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 102 103 /* Make sure required options are set */ 104 #ifndef CONFIG_SPD_EEPROM 105 #error ("CONFIG_SPD_EEPROM is required") 106 #endif 107 108 #undef CONFIG_CLOCKS_IN_MHZ 109 110 /* 111 * Local Bus Definitions 112 */ 113 114 /* 115 * FLASH on the Local Bus 116 * Two banks, 8M each, using the CFI driver. 117 * Boot from BR0/OR0 bank at 0xff00_0000 118 * Alternate BR1/OR1 bank at 0xff80_0000 119 * 120 * BR0, BR1: 121 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 122 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 123 * Port Size = 16 bits = BRx[19:20] = 10 124 * Use GPCM = BRx[24:26] = 000 125 * Valid = BRx[31] = 1 126 * 127 * 0 4 8 12 16 20 24 28 128 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 129 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 130 * 131 * OR0, OR1: 132 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 133 * Reserved ORx[17:18] = 11, confusion here? 134 * CSNT = ORx[20] = 1 135 * ACS = half cycle delay = ORx[21:22] = 11 136 * SCY = 6 = ORx[24:27] = 0110 137 * TRLX = use relaxed timing = ORx[29] = 1 138 * EAD = use external address latch delay = OR[31] = 1 139 * 140 * 0 4 8 12 16 20 24 28 141 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 142 */ 143 144 #define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ 145 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 146 147 #define CONFIG_SYS_BR0_PRELIM 0xff801001 148 #define CONFIG_SYS_BR1_PRELIM 0xff001001 149 150 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 151 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 152 153 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 154 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 155 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 156 #undef CONFIG_SYS_FLASH_CHECKSUM 157 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 158 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 159 160 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 161 162 #define CONFIG_FLASH_CFI_DRIVER 163 #define CONFIG_SYS_FLASH_CFI 164 #define CONFIG_SYS_FLASH_EMPTY_INFO 165 166 167 /* 168 * SDRAM on the Local Bus 169 */ 170 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 171 #define CONFIG_SYS_LBC_CACHE_SIZE 64 172 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ 173 #define CONFIG_SYS_LBC_NONCACHE_SIZE 64 174 175 #define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ 176 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 177 178 /* 179 * Base Register 2 and Option Register 2 configure SDRAM. 180 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 181 * 182 * For BR2, need: 183 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 184 * port-size = 32-bits = BR2[19:20] = 11 185 * no parity checking = BR2[21:22] = 00 186 * SDRAM for MSEL = BR2[24:26] = 011 187 * Valid = BR[31] = 1 188 * 189 * 0 4 8 12 16 20 24 28 190 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 191 * 192 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 193 * FIXME: the top 17 bits of BR2. 194 */ 195 196 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 197 198 /* 199 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 200 * 201 * For OR2, need: 202 * 64MB mask for AM, OR2[0:7] = 1111 1100 203 * XAM, OR2[17:18] = 11 204 * 9 columns OR2[19-21] = 010 205 * 13 rows OR2[23-25] = 100 206 * EAD set for extra time OR[31] = 1 207 * 208 * 0 4 8 12 16 20 24 28 209 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 210 */ 211 212 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 213 214 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 215 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 216 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 217 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 218 219 /* 220 * Common settings for all Local Bus SDRAM commands. 221 * At run time, either BSMA1516 (for CPU 1.1) 222 * or BSMA1617 (for CPU 1.0) (old) 223 * is OR'ed in too. 224 */ 225 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 226 | LSDMR_PRETOACT7 \ 227 | LSDMR_ACTTORW7 \ 228 | LSDMR_BL8 \ 229 | LSDMR_WRC4 \ 230 | LSDMR_CL3 \ 231 | LSDMR_RFEN \ 232 ) 233 234 /* 235 * The CADMUS registers are connected to CS3 on CDS. 236 * The new memory map places CADMUS at 0xf8000000. 237 * 238 * For BR3, need: 239 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 240 * port-size = 8-bits = BR[19:20] = 01 241 * no parity checking = BR[21:22] = 00 242 * GPMC for MSEL = BR[24:26] = 000 243 * Valid = BR[31] = 1 244 * 245 * 0 4 8 12 16 20 24 28 246 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 247 * 248 * For OR3, need: 249 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 250 * disable buffer ctrl OR[19] = 0 251 * CSNT OR[20] = 1 252 * ACS OR[21:22] = 11 253 * XACS OR[23] = 1 254 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 255 * SETA OR[28] = 0 256 * TRLX OR[29] = 1 257 * EHTR OR[30] = 1 258 * EAD extra time OR[31] = 1 259 * 260 * 0 4 8 12 16 20 24 28 261 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 262 */ 263 264 #define CONFIG_FSL_CADMUS 265 266 #define CADMUS_BASE_ADDR 0xf8000000 267 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 268 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 269 270 #define CONFIG_SYS_INIT_RAM_LOCK 1 271 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 272 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 273 274 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 275 276 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 277 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 278 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 279 280 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 281 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 282 283 /* Serial Port */ 284 #define CONFIG_CONS_INDEX 2 285 #undef CONFIG_SERIAL_SOFTWARE_FIFO 286 #define CONFIG_SYS_NS16550 287 #define CONFIG_SYS_NS16550_SERIAL 288 #define CONFIG_SYS_NS16550_REG_SIZE 1 289 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 290 291 #define CONFIG_SYS_BAUDRATE_TABLE \ 292 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 293 294 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 295 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 296 297 /* Use the HUSH parser */ 298 #define CONFIG_SYS_HUSH_PARSER 299 #ifdef CONFIG_SYS_HUSH_PARSER 300 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 301 #endif 302 303 /* pass open firmware flat tree */ 304 #define CONFIG_OF_LIBFDT 1 305 #define CONFIG_OF_BOARD_SETUP 1 306 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 307 308 /* 309 * I2C 310 */ 311 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 312 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 313 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 314 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 315 #define CONFIG_SYS_I2C_SLAVE 0x7F 316 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 317 #define CONFIG_SYS_I2C_OFFSET 0x3000 318 319 /* EEPROM */ 320 #define CONFIG_ID_EEPROM 321 #define CONFIG_SYS_I2C_EEPROM_CCID 322 #define CONFIG_SYS_ID_EEPROM 323 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 324 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 325 326 /* 327 * General PCI 328 * Memory space is mapped 1-1, but I/O space must start from 0. 329 */ 330 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 331 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 332 333 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 334 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 335 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 336 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 337 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 338 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 339 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 340 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 341 342 #ifdef CONFIG_PCI2 343 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 344 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 345 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 346 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 347 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 348 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 349 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 350 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 351 #endif 352 353 #ifdef CONFIG_PCIE1 354 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 355 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 356 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 357 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 358 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 359 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 360 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 361 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 362 #endif 363 364 #ifdef CONFIG_RIO 365 /* 366 * RapidIO MMU 367 */ 368 #define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 369 #define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 370 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 371 #endif 372 373 #ifdef CONFIG_LEGACY 374 #define BRIDGE_ID 17 375 #define VIA_ID 2 376 #else 377 #define BRIDGE_ID 28 378 #define VIA_ID 4 379 #endif 380 381 #if defined(CONFIG_PCI) 382 383 #define CONFIG_NET_MULTI 384 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 385 386 #undef CONFIG_EEPRO100 387 #undef CONFIG_TULIP 388 389 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 390 391 #endif /* CONFIG_PCI */ 392 393 394 #if defined(CONFIG_TSEC_ENET) 395 396 #ifndef CONFIG_NET_MULTI 397 #define CONFIG_NET_MULTI 1 398 #endif 399 400 #define CONFIG_MII 1 /* MII PHY management */ 401 #define CONFIG_TSEC1 1 402 #define CONFIG_TSEC1_NAME "eTSEC0" 403 #define CONFIG_TSEC2 1 404 #define CONFIG_TSEC2_NAME "eTSEC1" 405 #define CONFIG_TSEC3 1 406 #define CONFIG_TSEC3_NAME "eTSEC2" 407 #define CONFIG_TSEC4 408 #define CONFIG_TSEC4_NAME "eTSEC3" 409 #undef CONFIG_MPC85XX_FEC 410 411 #define TSEC1_PHY_ADDR 0 412 #define TSEC2_PHY_ADDR 1 413 #define TSEC3_PHY_ADDR 2 414 #define TSEC4_PHY_ADDR 3 415 416 #define TSEC1_PHYIDX 0 417 #define TSEC2_PHYIDX 0 418 #define TSEC3_PHYIDX 0 419 #define TSEC4_PHYIDX 0 420 #define TSEC1_FLAGS TSEC_GIGABIT 421 #define TSEC2_FLAGS TSEC_GIGABIT 422 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 423 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 424 425 /* Options are: eTSEC[0-3] */ 426 #define CONFIG_ETHPRIME "eTSEC0" 427 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 428 #endif /* CONFIG_TSEC_ENET */ 429 430 /* 431 * Environment 432 */ 433 #define CONFIG_ENV_IS_IN_FLASH 1 434 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 435 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 436 #define CONFIG_ENV_SIZE 0x2000 437 438 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 439 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 440 441 /* 442 * BOOTP options 443 */ 444 #define CONFIG_BOOTP_BOOTFILESIZE 445 #define CONFIG_BOOTP_BOOTPATH 446 #define CONFIG_BOOTP_GATEWAY 447 #define CONFIG_BOOTP_HOSTNAME 448 449 450 /* 451 * Command line configuration. 452 */ 453 #include <config_cmd_default.h> 454 455 #define CONFIG_CMD_PING 456 #define CONFIG_CMD_I2C 457 #define CONFIG_CMD_MII 458 #define CONFIG_CMD_ELF 459 #define CONFIG_CMD_IRQ 460 #define CONFIG_CMD_SETEXPR 461 #define CONFIG_CMD_REGINFO 462 463 #if defined(CONFIG_PCI) 464 #define CONFIG_CMD_PCI 465 #endif 466 467 468 #undef CONFIG_WATCHDOG /* watchdog disabled */ 469 470 /* 471 * Miscellaneous configurable options 472 */ 473 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 474 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 475 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 476 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 477 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 478 #if defined(CONFIG_CMD_KGDB) 479 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 480 #else 481 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 482 #endif 483 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 484 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 485 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 486 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 487 488 /* 489 * For booting Linux, the board info and command line data 490 * have to be in the first 16 MB of memory, since this is 491 * the maximum mapped by the Linux kernel during initialization. 492 */ 493 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 494 495 /* 496 * Internal Definitions 497 * 498 * Boot Flags 499 */ 500 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 501 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 502 503 #if defined(CONFIG_CMD_KGDB) 504 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 505 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 506 #endif 507 508 /* 509 * Environment Configuration 510 */ 511 512 /* The mac addresses for all ethernet interface */ 513 #if defined(CONFIG_TSEC_ENET) 514 #define CONFIG_HAS_ETH0 515 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 516 #define CONFIG_HAS_ETH1 517 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 518 #define CONFIG_HAS_ETH2 519 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 520 #define CONFIG_HAS_ETH3 521 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 522 #endif 523 524 #define CONFIG_IPADDR 192.168.1.253 525 526 #define CONFIG_HOSTNAME unknown 527 #define CONFIG_ROOTPATH /nfsroot 528 #define CONFIG_BOOTFILE 8548cds/uImage.uboot 529 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 530 531 #define CONFIG_SERVERIP 192.168.1.1 532 #define CONFIG_GATEWAYIP 192.168.1.1 533 #define CONFIG_NETMASK 255.255.255.0 534 535 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 536 537 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 538 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 539 540 #define CONFIG_BAUDRATE 115200 541 542 #define CONFIG_EXTRA_ENV_SETTINGS \ 543 "netdev=eth0\0" \ 544 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 545 "tftpflash=tftpboot $loadaddr $uboot; " \ 546 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 547 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 548 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 549 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 550 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 551 "consoledev=ttyS1\0" \ 552 "ramdiskaddr=2000000\0" \ 553 "ramdiskfile=ramdisk.uboot\0" \ 554 "fdtaddr=c00000\0" \ 555 "fdtfile=mpc8548cds.dtb\0" 556 557 #define CONFIG_NFSBOOTCOMMAND \ 558 "setenv bootargs root=/dev/nfs rw " \ 559 "nfsroot=$serverip:$rootpath " \ 560 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 561 "console=$consoledev,$baudrate $othbootargs;" \ 562 "tftp $loadaddr $bootfile;" \ 563 "tftp $fdtaddr $fdtfile;" \ 564 "bootm $loadaddr - $fdtaddr" 565 566 567 #define CONFIG_RAMBOOTCOMMAND \ 568 "setenv bootargs root=/dev/ram rw " \ 569 "console=$consoledev,$baudrate $othbootargs;" \ 570 "tftp $ramdiskaddr $ramdiskfile;" \ 571 "tftp $loadaddr $bootfile;" \ 572 "tftp $fdtaddr $fdtfile;" \ 573 "bootm $loadaddr $ramdiskaddr $fdtaddr" 574 575 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 576 577 #endif /* __CONFIG_H */ 578