1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8548cds board configuration file 8 * 9 * Please refer to doc/README.mpc85xxcds for more info. 10 * 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_SYS_SRIO 16 #define CONFIG_SRIO1 /* SRIO port 1 */ 17 18 #define CONFIG_PCI1 /* PCI controller 1 */ 19 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 20 #undef CONFIG_PCI2 21 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 22 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 23 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 25 26 #define CONFIG_ENV_OVERWRITE 27 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 28 29 #define CONFIG_FSL_VIA 30 31 #ifndef __ASSEMBLY__ 32 extern unsigned long get_clock_freq(void); 33 #endif 34 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 35 36 /* 37 * These can be toggled for performance analysis, otherwise use default. 38 */ 39 #define CONFIG_L2_CACHE /* toggle L2 cache */ 40 #define CONFIG_BTB /* toggle branch predition */ 41 42 /* 43 * Only possible on E500 Version 2 or newer cores. 44 */ 45 #define CONFIG_ENABLE_36BIT_PHYS 1 46 47 #ifdef CONFIG_PHYS_64BIT 48 #define CONFIG_ADDR_MAP 49 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 50 #endif 51 52 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 53 #define CONFIG_SYS_MEMTEST_END 0x00400000 54 55 #define CONFIG_SYS_CCSRBAR 0xe0000000 56 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 57 58 /* DDR Setup */ 59 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 60 #define CONFIG_DDR_SPD 61 62 #define CONFIG_DDR_ECC 63 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 64 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 65 66 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 67 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 68 69 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 70 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 71 72 /* I2C addresses of SPD EEPROMs */ 73 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 74 75 /* Make sure required options are set */ 76 #ifndef CONFIG_SPD_EEPROM 77 #error ("CONFIG_SPD_EEPROM is required") 78 #endif 79 80 #undef CONFIG_CLOCKS_IN_MHZ 81 /* 82 * Physical Address Map 83 * 84 * 32bit: 85 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 86 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 87 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 88 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 89 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 90 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 91 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 92 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 93 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 94 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 95 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 96 * 97 * 36bit: 98 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 99 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 100 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 101 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 102 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 103 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 104 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 105 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 106 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 107 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 108 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 109 * 110 */ 111 112 /* 113 * Local Bus Definitions 114 */ 115 116 /* 117 * FLASH on the Local Bus 118 * Two banks, 8M each, using the CFI driver. 119 * Boot from BR0/OR0 bank at 0xff00_0000 120 * Alternate BR1/OR1 bank at 0xff80_0000 121 * 122 * BR0, BR1: 123 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 124 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 125 * Port Size = 16 bits = BRx[19:20] = 10 126 * Use GPCM = BRx[24:26] = 000 127 * Valid = BRx[31] = 1 128 * 129 * 0 4 8 12 16 20 24 28 130 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 131 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 132 * 133 * OR0, OR1: 134 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 135 * Reserved ORx[17:18] = 11, confusion here? 136 * CSNT = ORx[20] = 1 137 * ACS = half cycle delay = ORx[21:22] = 11 138 * SCY = 6 = ORx[24:27] = 0110 139 * TRLX = use relaxed timing = ORx[29] = 1 140 * EAD = use external address latch delay = OR[31] = 1 141 * 142 * 0 4 8 12 16 20 24 28 143 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 144 */ 145 146 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 149 #else 150 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 151 #endif 152 153 #define CONFIG_SYS_BR0_PRELIM \ 154 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 155 #define CONFIG_SYS_BR1_PRELIM \ 156 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 157 158 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 159 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 160 161 #define CONFIG_SYS_FLASH_BANKS_LIST \ 162 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 163 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 164 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 165 #undef CONFIG_SYS_FLASH_CHECKSUM 166 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 167 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 168 169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 170 171 #define CONFIG_SYS_FLASH_EMPTY_INFO 172 173 #define CONFIG_HWCONFIG /* enable hwconfig */ 174 175 /* 176 * SDRAM on the Local Bus 177 */ 178 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 179 #ifdef CONFIG_PHYS_64BIT 180 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 181 #else 182 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 183 #endif 184 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 185 186 /* 187 * Base Register 2 and Option Register 2 configure SDRAM. 188 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 189 * 190 * For BR2, need: 191 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 192 * port-size = 32-bits = BR2[19:20] = 11 193 * no parity checking = BR2[21:22] = 00 194 * SDRAM for MSEL = BR2[24:26] = 011 195 * Valid = BR[31] = 1 196 * 197 * 0 4 8 12 16 20 24 28 198 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 199 * 200 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 201 * FIXME: the top 17 bits of BR2. 202 */ 203 204 #define CONFIG_SYS_BR2_PRELIM \ 205 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 206 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 207 208 /* 209 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 210 * 211 * For OR2, need: 212 * 64MB mask for AM, OR2[0:7] = 1111 1100 213 * XAM, OR2[17:18] = 11 214 * 9 columns OR2[19-21] = 010 215 * 13 rows OR2[23-25] = 100 216 * EAD set for extra time OR[31] = 1 217 * 218 * 0 4 8 12 16 20 24 28 219 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 220 */ 221 222 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 223 224 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 225 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 226 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 227 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 228 229 /* 230 * Common settings for all Local Bus SDRAM commands. 231 * At run time, either BSMA1516 (for CPU 1.1) 232 * or BSMA1617 (for CPU 1.0) (old) 233 * is OR'ed in too. 234 */ 235 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 236 | LSDMR_PRETOACT7 \ 237 | LSDMR_ACTTORW7 \ 238 | LSDMR_BL8 \ 239 | LSDMR_WRC4 \ 240 | LSDMR_CL3 \ 241 | LSDMR_RFEN \ 242 ) 243 244 /* 245 * The CADMUS registers are connected to CS3 on CDS. 246 * The new memory map places CADMUS at 0xf8000000. 247 * 248 * For BR3, need: 249 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 250 * port-size = 8-bits = BR[19:20] = 01 251 * no parity checking = BR[21:22] = 00 252 * GPMC for MSEL = BR[24:26] = 000 253 * Valid = BR[31] = 1 254 * 255 * 0 4 8 12 16 20 24 28 256 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 257 * 258 * For OR3, need: 259 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 260 * disable buffer ctrl OR[19] = 0 261 * CSNT OR[20] = 1 262 * ACS OR[21:22] = 11 263 * XACS OR[23] = 1 264 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 265 * SETA OR[28] = 0 266 * TRLX OR[29] = 1 267 * EHTR OR[30] = 1 268 * EAD extra time OR[31] = 1 269 * 270 * 0 4 8 12 16 20 24 28 271 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 272 */ 273 274 #define CONFIG_FSL_CADMUS 275 276 #define CADMUS_BASE_ADDR 0xf8000000 277 #ifdef CONFIG_PHYS_64BIT 278 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 279 #else 280 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 281 #endif 282 #define CONFIG_SYS_BR3_PRELIM \ 283 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 284 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 285 286 #define CONFIG_SYS_INIT_RAM_LOCK 1 287 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 288 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 289 290 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 291 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 292 293 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 294 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 295 296 /* Serial Port */ 297 #define CONFIG_SYS_NS16550_SERIAL 298 #define CONFIG_SYS_NS16550_REG_SIZE 1 299 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 300 301 #define CONFIG_SYS_BAUDRATE_TABLE \ 302 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 303 304 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 305 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 306 307 /* 308 * I2C 309 */ 310 #define CONFIG_SYS_I2C 311 #define CONFIG_SYS_I2C_FSL 312 #define CONFIG_SYS_FSL_I2C_SPEED 400000 313 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 314 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 315 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 316 317 /* EEPROM */ 318 #define CONFIG_ID_EEPROM 319 #define CONFIG_SYS_I2C_EEPROM_CCID 320 #define CONFIG_SYS_ID_EEPROM 321 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 322 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 323 324 /* 325 * General PCI 326 * Memory space is mapped 1-1, but I/O space must start from 0. 327 */ 328 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 329 #ifdef CONFIG_PHYS_64BIT 330 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 331 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 332 #else 333 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 334 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 335 #endif 336 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 337 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 338 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 339 #ifdef CONFIG_PHYS_64BIT 340 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 341 #else 342 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 343 #endif 344 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 345 346 #ifdef CONFIG_PCIE1 347 #define CONFIG_SYS_PCIE1_NAME "Slot" 348 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 349 #ifdef CONFIG_PHYS_64BIT 350 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 351 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 352 #else 353 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 354 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 355 #endif 356 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 357 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 358 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 359 #ifdef CONFIG_PHYS_64BIT 360 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 361 #else 362 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 363 #endif 364 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 365 #endif 366 367 /* 368 * RapidIO MMU 369 */ 370 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 371 #ifdef CONFIG_PHYS_64BIT 372 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 373 #else 374 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 375 #endif 376 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 377 378 #ifdef CONFIG_LEGACY 379 #define BRIDGE_ID 17 380 #define VIA_ID 2 381 #else 382 #define BRIDGE_ID 28 383 #define VIA_ID 4 384 #endif 385 386 #if defined(CONFIG_PCI) 387 #undef CONFIG_EEPRO100 388 #undef CONFIG_TULIP 389 390 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 391 392 #endif /* CONFIG_PCI */ 393 394 #if defined(CONFIG_TSEC_ENET) 395 396 #define CONFIG_TSEC1 1 397 #define CONFIG_TSEC1_NAME "eTSEC0" 398 #define CONFIG_TSEC2 1 399 #define CONFIG_TSEC2_NAME "eTSEC1" 400 #define CONFIG_TSEC3 1 401 #define CONFIG_TSEC3_NAME "eTSEC2" 402 #define CONFIG_TSEC4 403 #define CONFIG_TSEC4_NAME "eTSEC3" 404 #undef CONFIG_MPC85XX_FEC 405 406 #define TSEC1_PHY_ADDR 0 407 #define TSEC2_PHY_ADDR 1 408 #define TSEC3_PHY_ADDR 2 409 #define TSEC4_PHY_ADDR 3 410 411 #define TSEC1_PHYIDX 0 412 #define TSEC2_PHYIDX 0 413 #define TSEC3_PHYIDX 0 414 #define TSEC4_PHYIDX 0 415 #define TSEC1_FLAGS TSEC_GIGABIT 416 #define TSEC2_FLAGS TSEC_GIGABIT 417 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 418 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 419 420 /* Options are: eTSEC[0-3] */ 421 #define CONFIG_ETHPRIME "eTSEC0" 422 #endif /* CONFIG_TSEC_ENET */ 423 424 /* 425 * Environment 426 */ 427 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 428 #define CONFIG_ENV_ADDR 0xfff80000 429 #else 430 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 431 #endif 432 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 433 #define CONFIG_ENV_SIZE 0x2000 434 435 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 436 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 437 438 /* 439 * BOOTP options 440 */ 441 #define CONFIG_BOOTP_BOOTFILESIZE 442 443 #undef CONFIG_WATCHDOG /* watchdog disabled */ 444 445 /* 446 * Miscellaneous configurable options 447 */ 448 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 449 450 /* 451 * For booting Linux, the board info and command line data 452 * have to be in the first 64 MB of memory, since this is 453 * the maximum mapped by the Linux kernel during initialization. 454 */ 455 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 456 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 457 458 #if defined(CONFIG_CMD_KGDB) 459 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 460 #endif 461 462 /* 463 * Environment Configuration 464 */ 465 #if defined(CONFIG_TSEC_ENET) 466 #define CONFIG_HAS_ETH0 467 #define CONFIG_HAS_ETH1 468 #define CONFIG_HAS_ETH2 469 #define CONFIG_HAS_ETH3 470 #endif 471 472 #define CONFIG_IPADDR 192.168.1.253 473 474 #define CONFIG_HOSTNAME "unknown" 475 #define CONFIG_ROOTPATH "/nfsroot" 476 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 477 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 478 479 #define CONFIG_SERVERIP 192.168.1.1 480 #define CONFIG_GATEWAYIP 192.168.1.1 481 #define CONFIG_NETMASK 255.255.255.0 482 483 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 484 485 #define CONFIG_EXTRA_ENV_SETTINGS \ 486 "hwconfig=fsl_ddr:ecc=off\0" \ 487 "netdev=eth0\0" \ 488 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 489 "tftpflash=tftpboot $loadaddr $uboot; " \ 490 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 491 " +$filesize; " \ 492 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 493 " +$filesize; " \ 494 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 495 " $filesize; " \ 496 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 497 " +$filesize; " \ 498 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 499 " $filesize\0" \ 500 "consoledev=ttyS1\0" \ 501 "ramdiskaddr=2000000\0" \ 502 "ramdiskfile=ramdisk.uboot\0" \ 503 "fdtaddr=1e00000\0" \ 504 "fdtfile=mpc8548cds.dtb\0" 505 506 #define CONFIG_NFSBOOTCOMMAND \ 507 "setenv bootargs root=/dev/nfs rw " \ 508 "nfsroot=$serverip:$rootpath " \ 509 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 510 "console=$consoledev,$baudrate $othbootargs;" \ 511 "tftp $loadaddr $bootfile;" \ 512 "tftp $fdtaddr $fdtfile;" \ 513 "bootm $loadaddr - $fdtaddr" 514 515 #define CONFIG_RAMBOOTCOMMAND \ 516 "setenv bootargs root=/dev/ram rw " \ 517 "console=$consoledev,$baudrate $othbootargs;" \ 518 "tftp $ramdiskaddr $ramdiskfile;" \ 519 "tftp $loadaddr $bootfile;" \ 520 "tftp $fdtaddr $fdtfile;" \ 521 "bootm $loadaddr $ramdiskaddr $fdtaddr" 522 523 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 524 525 #endif /* __CONFIG_H */ 526