1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #ifndef CONFIG_SYS_TEXT_BASE 40 #define CONFIG_SYS_TEXT_BASE 0xfff80000 41 #endif 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 46 #define CONFIG_PCI /* enable any pci type devices */ 47 #define CONFIG_PCI1 /* PCI controller 1 */ 48 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 49 #undef CONFIG_PCI2 50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 51 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 52 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 57 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 58 59 #define CONFIG_FSL_VIA 60 61 #ifndef __ASSEMBLY__ 62 extern unsigned long get_clock_freq(void); 63 #endif 64 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 72 /* 73 * Only possible on E500 Version 2 or newer cores. 74 */ 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 78 #define CONFIG_SYS_MEMTEST_END 0x00400000 79 80 #define CONFIG_SYS_CCSRBAR 0xe0000000 81 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 82 83 /* DDR Setup */ 84 #define CONFIG_FSL_DDR2 85 #undef CONFIG_FSL_DDR_INTERACTIVE 86 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 87 #define CONFIG_DDR_SPD 88 89 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 90 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 91 92 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 94 95 #define CONFIG_NUM_DDR_CONTROLLERS 1 96 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 97 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 98 99 /* I2C addresses of SPD EEPROMs */ 100 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 101 102 /* Make sure required options are set */ 103 #ifndef CONFIG_SPD_EEPROM 104 #error ("CONFIG_SPD_EEPROM is required") 105 #endif 106 107 #undef CONFIG_CLOCKS_IN_MHZ 108 109 /* 110 * Local Bus Definitions 111 */ 112 113 /* 114 * FLASH on the Local Bus 115 * Two banks, 8M each, using the CFI driver. 116 * Boot from BR0/OR0 bank at 0xff00_0000 117 * Alternate BR1/OR1 bank at 0xff80_0000 118 * 119 * BR0, BR1: 120 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 121 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 122 * Port Size = 16 bits = BRx[19:20] = 10 123 * Use GPCM = BRx[24:26] = 000 124 * Valid = BRx[31] = 1 125 * 126 * 0 4 8 12 16 20 24 28 127 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 128 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 129 * 130 * OR0, OR1: 131 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 132 * Reserved ORx[17:18] = 11, confusion here? 133 * CSNT = ORx[20] = 1 134 * ACS = half cycle delay = ORx[21:22] = 11 135 * SCY = 6 = ORx[24:27] = 0110 136 * TRLX = use relaxed timing = ORx[29] = 1 137 * EAD = use external address latch delay = OR[31] = 1 138 * 139 * 0 4 8 12 16 20 24 28 140 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 141 */ 142 143 #define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ 144 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 145 146 #define CONFIG_SYS_BR0_PRELIM 0xff801001 147 #define CONFIG_SYS_BR1_PRELIM 0xff001001 148 149 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 150 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 151 152 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 153 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 154 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 155 #undef CONFIG_SYS_FLASH_CHECKSUM 156 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 157 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 158 159 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 160 161 #define CONFIG_FLASH_CFI_DRIVER 162 #define CONFIG_SYS_FLASH_CFI 163 #define CONFIG_SYS_FLASH_EMPTY_INFO 164 165 166 /* 167 * SDRAM on the Local Bus 168 */ 169 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 170 #define CONFIG_SYS_LBC_CACHE_SIZE 64 171 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ 172 #define CONFIG_SYS_LBC_NONCACHE_SIZE 64 173 174 #define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ 175 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 176 177 /* 178 * Base Register 2 and Option Register 2 configure SDRAM. 179 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 180 * 181 * For BR2, need: 182 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 183 * port-size = 32-bits = BR2[19:20] = 11 184 * no parity checking = BR2[21:22] = 00 185 * SDRAM for MSEL = BR2[24:26] = 011 186 * Valid = BR[31] = 1 187 * 188 * 0 4 8 12 16 20 24 28 189 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 190 * 191 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 192 * FIXME: the top 17 bits of BR2. 193 */ 194 195 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 196 197 /* 198 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 199 * 200 * For OR2, need: 201 * 64MB mask for AM, OR2[0:7] = 1111 1100 202 * XAM, OR2[17:18] = 11 203 * 9 columns OR2[19-21] = 010 204 * 13 rows OR2[23-25] = 100 205 * EAD set for extra time OR[31] = 1 206 * 207 * 0 4 8 12 16 20 24 28 208 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 209 */ 210 211 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 212 213 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 214 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 215 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 216 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 217 218 /* 219 * Common settings for all Local Bus SDRAM commands. 220 * At run time, either BSMA1516 (for CPU 1.1) 221 * or BSMA1617 (for CPU 1.0) (old) 222 * is OR'ed in too. 223 */ 224 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 225 | LSDMR_PRETOACT7 \ 226 | LSDMR_ACTTORW7 \ 227 | LSDMR_BL8 \ 228 | LSDMR_WRC4 \ 229 | LSDMR_CL3 \ 230 | LSDMR_RFEN \ 231 ) 232 233 /* 234 * The CADMUS registers are connected to CS3 on CDS. 235 * The new memory map places CADMUS at 0xf8000000. 236 * 237 * For BR3, need: 238 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 239 * port-size = 8-bits = BR[19:20] = 01 240 * no parity checking = BR[21:22] = 00 241 * GPMC for MSEL = BR[24:26] = 000 242 * Valid = BR[31] = 1 243 * 244 * 0 4 8 12 16 20 24 28 245 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 246 * 247 * For OR3, need: 248 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 249 * disable buffer ctrl OR[19] = 0 250 * CSNT OR[20] = 1 251 * ACS OR[21:22] = 11 252 * XACS OR[23] = 1 253 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 254 * SETA OR[28] = 0 255 * TRLX OR[29] = 1 256 * EHTR OR[30] = 1 257 * EAD extra time OR[31] = 1 258 * 259 * 0 4 8 12 16 20 24 28 260 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 261 */ 262 263 #define CONFIG_FSL_CADMUS 264 265 #define CADMUS_BASE_ADDR 0xf8000000 266 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 267 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 268 269 #define CONFIG_SYS_INIT_RAM_LOCK 1 270 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 271 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 272 273 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 274 275 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 276 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 277 278 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 279 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 280 281 /* Serial Port */ 282 #define CONFIG_CONS_INDEX 2 283 #define CONFIG_SYS_NS16550 284 #define CONFIG_SYS_NS16550_SERIAL 285 #define CONFIG_SYS_NS16550_REG_SIZE 1 286 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 287 288 #define CONFIG_SYS_BAUDRATE_TABLE \ 289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 290 291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 293 294 /* Use the HUSH parser */ 295 #define CONFIG_SYS_HUSH_PARSER 296 #ifdef CONFIG_SYS_HUSH_PARSER 297 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 298 #endif 299 300 /* pass open firmware flat tree */ 301 #define CONFIG_OF_LIBFDT 1 302 #define CONFIG_OF_BOARD_SETUP 1 303 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 304 305 /* 306 * I2C 307 */ 308 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 309 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 310 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 311 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 312 #define CONFIG_SYS_I2C_SLAVE 0x7F 313 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 314 #define CONFIG_SYS_I2C_OFFSET 0x3000 315 316 /* EEPROM */ 317 #define CONFIG_ID_EEPROM 318 #define CONFIG_SYS_I2C_EEPROM_CCID 319 #define CONFIG_SYS_ID_EEPROM 320 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 321 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 322 323 /* 324 * General PCI 325 * Memory space is mapped 1-1, but I/O space must start from 0. 326 */ 327 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 328 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 329 330 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 331 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 332 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 333 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 334 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 335 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 336 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 337 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 338 339 #ifdef CONFIG_PCI2 340 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 341 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 342 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 343 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 344 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 345 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 346 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 347 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 348 #endif 349 350 #ifdef CONFIG_PCIE1 351 #define CONFIG_SYS_PCIE1_NAME "Slot" 352 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 353 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 354 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 355 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 356 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 357 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 358 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 359 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 360 #endif 361 362 /* 363 * RapidIO MMU 364 */ 365 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 366 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 367 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 368 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 369 370 #ifdef CONFIG_LEGACY 371 #define BRIDGE_ID 17 372 #define VIA_ID 2 373 #else 374 #define BRIDGE_ID 28 375 #define VIA_ID 4 376 #endif 377 378 #if defined(CONFIG_PCI) 379 380 #define CONFIG_NET_MULTI 381 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 382 383 #undef CONFIG_EEPRO100 384 #undef CONFIG_TULIP 385 386 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 387 388 #endif /* CONFIG_PCI */ 389 390 391 #if defined(CONFIG_TSEC_ENET) 392 393 #ifndef CONFIG_NET_MULTI 394 #define CONFIG_NET_MULTI 1 395 #endif 396 397 #define CONFIG_MII 1 /* MII PHY management */ 398 #define CONFIG_TSEC1 1 399 #define CONFIG_TSEC1_NAME "eTSEC0" 400 #define CONFIG_TSEC2 1 401 #define CONFIG_TSEC2_NAME "eTSEC1" 402 #define CONFIG_TSEC3 1 403 #define CONFIG_TSEC3_NAME "eTSEC2" 404 #define CONFIG_TSEC4 405 #define CONFIG_TSEC4_NAME "eTSEC3" 406 #undef CONFIG_MPC85XX_FEC 407 408 #define TSEC1_PHY_ADDR 0 409 #define TSEC2_PHY_ADDR 1 410 #define TSEC3_PHY_ADDR 2 411 #define TSEC4_PHY_ADDR 3 412 413 #define TSEC1_PHYIDX 0 414 #define TSEC2_PHYIDX 0 415 #define TSEC3_PHYIDX 0 416 #define TSEC4_PHYIDX 0 417 #define TSEC1_FLAGS TSEC_GIGABIT 418 #define TSEC2_FLAGS TSEC_GIGABIT 419 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 420 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 421 422 /* Options are: eTSEC[0-3] */ 423 #define CONFIG_ETHPRIME "eTSEC0" 424 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 425 #endif /* CONFIG_TSEC_ENET */ 426 427 /* 428 * Environment 429 */ 430 #define CONFIG_ENV_IS_IN_FLASH 1 431 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 432 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 433 #define CONFIG_ENV_SIZE 0x2000 434 435 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 436 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 437 438 /* 439 * BOOTP options 440 */ 441 #define CONFIG_BOOTP_BOOTFILESIZE 442 #define CONFIG_BOOTP_BOOTPATH 443 #define CONFIG_BOOTP_GATEWAY 444 #define CONFIG_BOOTP_HOSTNAME 445 446 447 /* 448 * Command line configuration. 449 */ 450 #include <config_cmd_default.h> 451 452 #define CONFIG_CMD_PING 453 #define CONFIG_CMD_I2C 454 #define CONFIG_CMD_MII 455 #define CONFIG_CMD_ELF 456 #define CONFIG_CMD_IRQ 457 #define CONFIG_CMD_SETEXPR 458 #define CONFIG_CMD_REGINFO 459 460 #if defined(CONFIG_PCI) 461 #define CONFIG_CMD_PCI 462 #endif 463 464 465 #undef CONFIG_WATCHDOG /* watchdog disabled */ 466 467 /* 468 * Miscellaneous configurable options 469 */ 470 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 471 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 472 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 473 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 474 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 475 #if defined(CONFIG_CMD_KGDB) 476 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 477 #else 478 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 479 #endif 480 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 481 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 482 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 483 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 484 485 /* 486 * For booting Linux, the board info and command line data 487 * have to be in the first 64 MB of memory, since this is 488 * the maximum mapped by the Linux kernel during initialization. 489 */ 490 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 491 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 492 493 #if defined(CONFIG_CMD_KGDB) 494 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 495 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 496 #endif 497 498 /* 499 * Environment Configuration 500 */ 501 502 /* The mac addresses for all ethernet interface */ 503 #if defined(CONFIG_TSEC_ENET) 504 #define CONFIG_HAS_ETH0 505 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 506 #define CONFIG_HAS_ETH1 507 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 508 #define CONFIG_HAS_ETH2 509 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 510 #define CONFIG_HAS_ETH3 511 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 512 #endif 513 514 #define CONFIG_IPADDR 192.168.1.253 515 516 #define CONFIG_HOSTNAME unknown 517 #define CONFIG_ROOTPATH /nfsroot 518 #define CONFIG_BOOTFILE 8548cds/uImage.uboot 519 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 520 521 #define CONFIG_SERVERIP 192.168.1.1 522 #define CONFIG_GATEWAYIP 192.168.1.1 523 #define CONFIG_NETMASK 255.255.255.0 524 525 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 526 527 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 528 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 529 530 #define CONFIG_BAUDRATE 115200 531 532 #define CONFIG_EXTRA_ENV_SETTINGS \ 533 "netdev=eth0\0" \ 534 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 535 "tftpflash=tftpboot $loadaddr $uboot; " \ 536 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 537 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 538 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 539 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 540 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 541 "consoledev=ttyS1\0" \ 542 "ramdiskaddr=2000000\0" \ 543 "ramdiskfile=ramdisk.uboot\0" \ 544 "fdtaddr=c00000\0" \ 545 "fdtfile=mpc8548cds.dtb\0" 546 547 #define CONFIG_NFSBOOTCOMMAND \ 548 "setenv bootargs root=/dev/nfs rw " \ 549 "nfsroot=$serverip:$rootpath " \ 550 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 551 "console=$consoledev,$baudrate $othbootargs;" \ 552 "tftp $loadaddr $bootfile;" \ 553 "tftp $fdtaddr $fdtfile;" \ 554 "bootm $loadaddr - $fdtaddr" 555 556 557 #define CONFIG_RAMBOOTCOMMAND \ 558 "setenv bootargs root=/dev/ram rw " \ 559 "console=$consoledev,$baudrate $othbootargs;" \ 560 "tftp $ramdiskaddr $ramdiskfile;" \ 561 "tftp $loadaddr $bootfile;" \ 562 "tftp $fdtaddr $fdtfile;" \ 563 "bootm $loadaddr $ramdiskaddr $fdtaddr" 564 565 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 566 567 #endif /* __CONFIG_H */ 568