1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 20 #ifndef CONFIG_SYS_TEXT_BASE 21 #define CONFIG_SYS_TEXT_BASE 0xfff80000 22 #endif 23 24 #define CONFIG_SYS_SRIO 25 #define CONFIG_SRIO1 /* SRIO port 1 */ 26 27 #define CONFIG_PCI1 /* PCI controller 1 */ 28 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 29 #undef CONFIG_PCI2 30 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 32 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 34 35 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 36 #define CONFIG_ENV_OVERWRITE 37 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 38 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 39 40 #define CONFIG_FSL_VIA 41 42 #ifndef __ASSEMBLY__ 43 extern unsigned long get_clock_freq(void); 44 #endif 45 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 46 47 /* 48 * These can be toggled for performance analysis, otherwise use default. 49 */ 50 #define CONFIG_L2_CACHE /* toggle L2 cache */ 51 #define CONFIG_BTB /* toggle branch predition */ 52 53 /* 54 * Only possible on E500 Version 2 or newer cores. 55 */ 56 #define CONFIG_ENABLE_36BIT_PHYS 1 57 58 #ifdef CONFIG_PHYS_64BIT 59 #define CONFIG_ADDR_MAP 60 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 61 #endif 62 63 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 64 #define CONFIG_SYS_MEMTEST_END 0x00400000 65 66 #define CONFIG_SYS_CCSRBAR 0xe0000000 67 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 68 69 /* DDR Setup */ 70 #define CONFIG_SYS_FSL_DDR2 71 #undef CONFIG_FSL_DDR_INTERACTIVE 72 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 73 #define CONFIG_DDR_SPD 74 75 #define CONFIG_DDR_ECC 76 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 77 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 78 79 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 80 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 81 82 #define CONFIG_NUM_DDR_CONTROLLERS 1 83 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 84 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 85 86 /* I2C addresses of SPD EEPROMs */ 87 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 88 89 /* Make sure required options are set */ 90 #ifndef CONFIG_SPD_EEPROM 91 #error ("CONFIG_SPD_EEPROM is required") 92 #endif 93 94 #undef CONFIG_CLOCKS_IN_MHZ 95 /* 96 * Physical Address Map 97 * 98 * 32bit: 99 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 100 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 101 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 102 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 103 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 104 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 105 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 106 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 107 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 108 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 109 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 110 * 111 * 36bit: 112 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 113 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 114 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 115 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 116 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 117 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 118 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 119 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 120 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 121 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 122 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 123 * 124 */ 125 126 /* 127 * Local Bus Definitions 128 */ 129 130 /* 131 * FLASH on the Local Bus 132 * Two banks, 8M each, using the CFI driver. 133 * Boot from BR0/OR0 bank at 0xff00_0000 134 * Alternate BR1/OR1 bank at 0xff80_0000 135 * 136 * BR0, BR1: 137 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 138 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 139 * Port Size = 16 bits = BRx[19:20] = 10 140 * Use GPCM = BRx[24:26] = 000 141 * Valid = BRx[31] = 1 142 * 143 * 0 4 8 12 16 20 24 28 144 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 145 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 146 * 147 * OR0, OR1: 148 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 149 * Reserved ORx[17:18] = 11, confusion here? 150 * CSNT = ORx[20] = 1 151 * ACS = half cycle delay = ORx[21:22] = 11 152 * SCY = 6 = ORx[24:27] = 0110 153 * TRLX = use relaxed timing = ORx[29] = 1 154 * EAD = use external address latch delay = OR[31] = 1 155 * 156 * 0 4 8 12 16 20 24 28 157 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 158 */ 159 160 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 161 #ifdef CONFIG_PHYS_64BIT 162 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 163 #else 164 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 165 #endif 166 167 #define CONFIG_SYS_BR0_PRELIM \ 168 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 169 #define CONFIG_SYS_BR1_PRELIM \ 170 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 171 172 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 173 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 174 175 #define CONFIG_SYS_FLASH_BANKS_LIST \ 176 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 177 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 178 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 179 #undef CONFIG_SYS_FLASH_CHECKSUM 180 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 181 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 182 183 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 184 185 #define CONFIG_FLASH_CFI_DRIVER 186 #define CONFIG_SYS_FLASH_CFI 187 #define CONFIG_SYS_FLASH_EMPTY_INFO 188 189 #define CONFIG_HWCONFIG /* enable hwconfig */ 190 191 /* 192 * SDRAM on the Local Bus 193 */ 194 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 195 #ifdef CONFIG_PHYS_64BIT 196 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 197 #else 198 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 199 #endif 200 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 201 202 /* 203 * Base Register 2 and Option Register 2 configure SDRAM. 204 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 205 * 206 * For BR2, need: 207 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 208 * port-size = 32-bits = BR2[19:20] = 11 209 * no parity checking = BR2[21:22] = 00 210 * SDRAM for MSEL = BR2[24:26] = 011 211 * Valid = BR[31] = 1 212 * 213 * 0 4 8 12 16 20 24 28 214 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 215 * 216 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 217 * FIXME: the top 17 bits of BR2. 218 */ 219 220 #define CONFIG_SYS_BR2_PRELIM \ 221 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 222 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 223 224 /* 225 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 226 * 227 * For OR2, need: 228 * 64MB mask for AM, OR2[0:7] = 1111 1100 229 * XAM, OR2[17:18] = 11 230 * 9 columns OR2[19-21] = 010 231 * 13 rows OR2[23-25] = 100 232 * EAD set for extra time OR[31] = 1 233 * 234 * 0 4 8 12 16 20 24 28 235 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 236 */ 237 238 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 239 240 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 241 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 242 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 243 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 244 245 /* 246 * Common settings for all Local Bus SDRAM commands. 247 * At run time, either BSMA1516 (for CPU 1.1) 248 * or BSMA1617 (for CPU 1.0) (old) 249 * is OR'ed in too. 250 */ 251 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 252 | LSDMR_PRETOACT7 \ 253 | LSDMR_ACTTORW7 \ 254 | LSDMR_BL8 \ 255 | LSDMR_WRC4 \ 256 | LSDMR_CL3 \ 257 | LSDMR_RFEN \ 258 ) 259 260 /* 261 * The CADMUS registers are connected to CS3 on CDS. 262 * The new memory map places CADMUS at 0xf8000000. 263 * 264 * For BR3, need: 265 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 266 * port-size = 8-bits = BR[19:20] = 01 267 * no parity checking = BR[21:22] = 00 268 * GPMC for MSEL = BR[24:26] = 000 269 * Valid = BR[31] = 1 270 * 271 * 0 4 8 12 16 20 24 28 272 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 273 * 274 * For OR3, need: 275 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 276 * disable buffer ctrl OR[19] = 0 277 * CSNT OR[20] = 1 278 * ACS OR[21:22] = 11 279 * XACS OR[23] = 1 280 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 281 * SETA OR[28] = 0 282 * TRLX OR[29] = 1 283 * EHTR OR[30] = 1 284 * EAD extra time OR[31] = 1 285 * 286 * 0 4 8 12 16 20 24 28 287 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 288 */ 289 290 #define CONFIG_FSL_CADMUS 291 292 #define CADMUS_BASE_ADDR 0xf8000000 293 #ifdef CONFIG_PHYS_64BIT 294 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 295 #else 296 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 297 #endif 298 #define CONFIG_SYS_BR3_PRELIM \ 299 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 300 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 301 302 #define CONFIG_SYS_INIT_RAM_LOCK 1 303 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 304 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 305 306 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 307 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 308 309 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 310 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 311 312 /* Serial Port */ 313 #define CONFIG_CONS_INDEX 2 314 #define CONFIG_SYS_NS16550_SERIAL 315 #define CONFIG_SYS_NS16550_REG_SIZE 1 316 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 317 318 #define CONFIG_SYS_BAUDRATE_TABLE \ 319 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 320 321 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 322 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 323 324 /* 325 * I2C 326 */ 327 #define CONFIG_SYS_I2C 328 #define CONFIG_SYS_I2C_FSL 329 #define CONFIG_SYS_FSL_I2C_SPEED 400000 330 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 331 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 332 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 333 334 /* EEPROM */ 335 #define CONFIG_ID_EEPROM 336 #define CONFIG_SYS_I2C_EEPROM_CCID 337 #define CONFIG_SYS_ID_EEPROM 338 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 339 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 340 341 /* 342 * General PCI 343 * Memory space is mapped 1-1, but I/O space must start from 0. 344 */ 345 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 346 #ifdef CONFIG_PHYS_64BIT 347 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 348 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 349 #else 350 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 351 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 352 #endif 353 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 354 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 355 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 356 #ifdef CONFIG_PHYS_64BIT 357 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 358 #else 359 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 360 #endif 361 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 362 363 #ifdef CONFIG_PCIE1 364 #define CONFIG_SYS_PCIE1_NAME "Slot" 365 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 366 #ifdef CONFIG_PHYS_64BIT 367 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 368 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 369 #else 370 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 371 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 372 #endif 373 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 374 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 375 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 376 #ifdef CONFIG_PHYS_64BIT 377 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 378 #else 379 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 380 #endif 381 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 382 #endif 383 384 /* 385 * RapidIO MMU 386 */ 387 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 388 #ifdef CONFIG_PHYS_64BIT 389 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 390 #else 391 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 392 #endif 393 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 394 395 #ifdef CONFIG_LEGACY 396 #define BRIDGE_ID 17 397 #define VIA_ID 2 398 #else 399 #define BRIDGE_ID 28 400 #define VIA_ID 4 401 #endif 402 403 #if defined(CONFIG_PCI) 404 #undef CONFIG_EEPRO100 405 #undef CONFIG_TULIP 406 407 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 408 409 #endif /* CONFIG_PCI */ 410 411 #if defined(CONFIG_TSEC_ENET) 412 413 #define CONFIG_MII 1 /* MII PHY management */ 414 #define CONFIG_TSEC1 1 415 #define CONFIG_TSEC1_NAME "eTSEC0" 416 #define CONFIG_TSEC2 1 417 #define CONFIG_TSEC2_NAME "eTSEC1" 418 #define CONFIG_TSEC3 1 419 #define CONFIG_TSEC3_NAME "eTSEC2" 420 #define CONFIG_TSEC4 421 #define CONFIG_TSEC4_NAME "eTSEC3" 422 #undef CONFIG_MPC85XX_FEC 423 424 #define CONFIG_PHY_MARVELL 425 426 #define TSEC1_PHY_ADDR 0 427 #define TSEC2_PHY_ADDR 1 428 #define TSEC3_PHY_ADDR 2 429 #define TSEC4_PHY_ADDR 3 430 431 #define TSEC1_PHYIDX 0 432 #define TSEC2_PHYIDX 0 433 #define TSEC3_PHYIDX 0 434 #define TSEC4_PHYIDX 0 435 #define TSEC1_FLAGS TSEC_GIGABIT 436 #define TSEC2_FLAGS TSEC_GIGABIT 437 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 438 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 439 440 /* Options are: eTSEC[0-3] */ 441 #define CONFIG_ETHPRIME "eTSEC0" 442 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 443 #endif /* CONFIG_TSEC_ENET */ 444 445 /* 446 * Environment 447 */ 448 #define CONFIG_ENV_IS_IN_FLASH 1 449 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 450 #define CONFIG_ENV_ADDR 0xfff80000 451 #else 452 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 453 #endif 454 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 455 #define CONFIG_ENV_SIZE 0x2000 456 457 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 458 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 459 460 /* 461 * BOOTP options 462 */ 463 #define CONFIG_BOOTP_BOOTFILESIZE 464 #define CONFIG_BOOTP_BOOTPATH 465 #define CONFIG_BOOTP_GATEWAY 466 #define CONFIG_BOOTP_HOSTNAME 467 468 /* 469 * Command line configuration. 470 */ 471 #define CONFIG_CMD_IRQ 472 #define CONFIG_CMD_REGINFO 473 474 #if defined(CONFIG_PCI) 475 #define CONFIG_CMD_PCI 476 #endif 477 478 #undef CONFIG_WATCHDOG /* watchdog disabled */ 479 480 /* 481 * Miscellaneous configurable options 482 */ 483 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 484 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 485 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 486 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 487 #if defined(CONFIG_CMD_KGDB) 488 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 489 #else 490 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 491 #endif 492 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 493 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 494 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 495 496 /* 497 * For booting Linux, the board info and command line data 498 * have to be in the first 64 MB of memory, since this is 499 * the maximum mapped by the Linux kernel during initialization. 500 */ 501 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 502 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 503 504 #if defined(CONFIG_CMD_KGDB) 505 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 506 #endif 507 508 /* 509 * Environment Configuration 510 */ 511 #if defined(CONFIG_TSEC_ENET) 512 #define CONFIG_HAS_ETH0 513 #define CONFIG_HAS_ETH1 514 #define CONFIG_HAS_ETH2 515 #define CONFIG_HAS_ETH3 516 #endif 517 518 #define CONFIG_IPADDR 192.168.1.253 519 520 #define CONFIG_HOSTNAME unknown 521 #define CONFIG_ROOTPATH "/nfsroot" 522 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 523 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 524 525 #define CONFIG_SERVERIP 192.168.1.1 526 #define CONFIG_GATEWAYIP 192.168.1.1 527 #define CONFIG_NETMASK 255.255.255.0 528 529 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 530 531 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 532 533 #define CONFIG_BAUDRATE 115200 534 535 #define CONFIG_EXTRA_ENV_SETTINGS \ 536 "hwconfig=fsl_ddr:ecc=off\0" \ 537 "netdev=eth0\0" \ 538 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 539 "tftpflash=tftpboot $loadaddr $uboot; " \ 540 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 541 " +$filesize; " \ 542 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 543 " +$filesize; " \ 544 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 545 " $filesize; " \ 546 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 547 " +$filesize; " \ 548 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 549 " $filesize\0" \ 550 "consoledev=ttyS1\0" \ 551 "ramdiskaddr=2000000\0" \ 552 "ramdiskfile=ramdisk.uboot\0" \ 553 "fdtaddr=1e00000\0" \ 554 "fdtfile=mpc8548cds.dtb\0" 555 556 #define CONFIG_NFSBOOTCOMMAND \ 557 "setenv bootargs root=/dev/nfs rw " \ 558 "nfsroot=$serverip:$rootpath " \ 559 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 560 "console=$consoledev,$baudrate $othbootargs;" \ 561 "tftp $loadaddr $bootfile;" \ 562 "tftp $fdtaddr $fdtfile;" \ 563 "bootm $loadaddr - $fdtaddr" 564 565 #define CONFIG_RAMBOOTCOMMAND \ 566 "setenv bootargs root=/dev/ram rw " \ 567 "console=$consoledev,$baudrate $othbootargs;" \ 568 "tftp $ramdiskaddr $ramdiskfile;" \ 569 "tftp $loadaddr $bootfile;" \ 570 "tftp $fdtaddr $fdtfile;" \ 571 "bootm $loadaddr $ramdiskaddr $fdtaddr" 572 573 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 574 575 #endif /* __CONFIG_H */ 576