1 /* 2 * Copyright 2004, 2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #define CONFIG_PCI /* enable any pci type devices */ 40 #define CONFIG_PCI1 /* PCI controller 1 */ 41 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 42 #undef CONFIG_RIO 43 #undef CONFIG_PCI2 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 46 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 47 48 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 49 #define CONFIG_ENV_OVERWRITE 50 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 52 53 #define CONFIG_FSL_VIA 54 55 /* 56 * When initializing flash, if we cannot find the manufacturer ID, 57 * assume this is the AMD flash associated with the CDS board. 58 * This allows booting from a promjet. 59 */ 60 #define CONFIG_ASSUME_AMD_FLASH 61 62 #ifndef __ASSEMBLY__ 63 extern unsigned long get_clock_freq(void); 64 #endif 65 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 66 67 /* 68 * These can be toggled for performance analysis, otherwise use default. 69 */ 70 #define CONFIG_L2_CACHE /* toggle L2 cache */ 71 #define CONFIG_BTB /* toggle branch predition */ 72 73 /* 74 * Only possible on E500 Version 2 or newer cores. 75 */ 76 #define CONFIG_ENABLE_36BIT_PHYS 1 77 78 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 79 #define CONFIG_SYS_MEMTEST_END 0x00400000 80 81 /* 82 * Base addresses -- Note these are effective addresses where the 83 * actual resources get mapped (not physical addresses) 84 */ 85 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 86 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 87 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 88 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 89 90 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 91 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 92 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 93 94 /* DDR Setup */ 95 #define CONFIG_FSL_DDR2 96 #undef CONFIG_FSL_DDR_INTERACTIVE 97 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 98 #define CONFIG_DDR_SPD 99 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 100 101 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 102 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 103 104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 110 111 /* I2C addresses of SPD EEPROMs */ 112 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 113 114 /* Make sure required options are set */ 115 #ifndef CONFIG_SPD_EEPROM 116 #error ("CONFIG_SPD_EEPROM is required") 117 #endif 118 119 #undef CONFIG_CLOCKS_IN_MHZ 120 121 /* 122 * Local Bus Definitions 123 */ 124 125 /* 126 * FLASH on the Local Bus 127 * Two banks, 8M each, using the CFI driver. 128 * Boot from BR0/OR0 bank at 0xff00_0000 129 * Alternate BR1/OR1 bank at 0xff80_0000 130 * 131 * BR0, BR1: 132 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 133 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 134 * Port Size = 16 bits = BRx[19:20] = 10 135 * Use GPCM = BRx[24:26] = 000 136 * Valid = BRx[31] = 1 137 * 138 * 0 4 8 12 16 20 24 28 139 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 140 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 141 * 142 * OR0, OR1: 143 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 144 * Reserved ORx[17:18] = 11, confusion here? 145 * CSNT = ORx[20] = 1 146 * ACS = half cycle delay = ORx[21:22] = 11 147 * SCY = 6 = ORx[24:27] = 0110 148 * TRLX = use relaxed timing = ORx[29] = 1 149 * EAD = use external address latch delay = OR[31] = 1 150 * 151 * 0 4 8 12 16 20 24 28 152 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 153 */ 154 155 #define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ 156 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 157 158 #define CONFIG_SYS_BR0_PRELIM 0xff801001 159 #define CONFIG_SYS_BR1_PRELIM 0xff001001 160 161 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 162 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 163 164 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 165 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 166 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 167 #undef CONFIG_SYS_FLASH_CHECKSUM 168 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 169 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 170 171 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 172 173 #define CONFIG_FLASH_CFI_DRIVER 174 #define CONFIG_SYS_FLASH_CFI 175 #define CONFIG_SYS_FLASH_EMPTY_INFO 176 177 178 /* 179 * SDRAM on the Local Bus 180 */ 181 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 182 #define CONFIG_SYS_LBC_CACHE_SIZE 64 183 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ 184 #define CONFIG_SYS_LBC_NONCACHE_SIZE 64 185 186 #define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ 187 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 188 189 /* 190 * Base Register 2 and Option Register 2 configure SDRAM. 191 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 192 * 193 * For BR2, need: 194 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 195 * port-size = 32-bits = BR2[19:20] = 11 196 * no parity checking = BR2[21:22] = 00 197 * SDRAM for MSEL = BR2[24:26] = 011 198 * Valid = BR[31] = 1 199 * 200 * 0 4 8 12 16 20 24 28 201 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 202 * 203 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 204 * FIXME: the top 17 bits of BR2. 205 */ 206 207 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 208 209 /* 210 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 211 * 212 * For OR2, need: 213 * 64MB mask for AM, OR2[0:7] = 1111 1100 214 * XAM, OR2[17:18] = 11 215 * 9 columns OR2[19-21] = 010 216 * 13 rows OR2[23-25] = 100 217 * EAD set for extra time OR[31] = 1 218 * 219 * 0 4 8 12 16 20 24 28 220 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 221 */ 222 223 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 224 225 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 226 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 227 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 228 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 229 230 /* 231 * Common settings for all Local Bus SDRAM commands. 232 * At run time, either BSMA1516 (for CPU 1.1) 233 * or BSMA1617 (for CPU 1.0) (old) 234 * is OR'ed in too. 235 */ 236 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 237 | LSDMR_PRETOACT7 \ 238 | LSDMR_ACTTORW7 \ 239 | LSDMR_BL8 \ 240 | LSDMR_WRC4 \ 241 | LSDMR_CL3 \ 242 | LSDMR_RFEN \ 243 ) 244 245 /* 246 * The CADMUS registers are connected to CS3 on CDS. 247 * The new memory map places CADMUS at 0xf8000000. 248 * 249 * For BR3, need: 250 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 251 * port-size = 8-bits = BR[19:20] = 01 252 * no parity checking = BR[21:22] = 00 253 * GPMC for MSEL = BR[24:26] = 000 254 * Valid = BR[31] = 1 255 * 256 * 0 4 8 12 16 20 24 28 257 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 258 * 259 * For OR3, need: 260 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 261 * disable buffer ctrl OR[19] = 0 262 * CSNT OR[20] = 1 263 * ACS OR[21:22] = 11 264 * XACS OR[23] = 1 265 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 266 * SETA OR[28] = 0 267 * TRLX OR[29] = 1 268 * EHTR OR[30] = 1 269 * EAD extra time OR[31] = 1 270 * 271 * 0 4 8 12 16 20 24 28 272 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 273 */ 274 275 #define CONFIG_FSL_CADMUS 276 277 #define CADMUS_BASE_ADDR 0xf8000000 278 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 279 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 280 281 #define CONFIG_SYS_INIT_RAM_LOCK 1 282 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 283 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 284 285 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 286 287 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 288 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 289 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 290 291 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 292 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 293 294 /* Serial Port */ 295 #define CONFIG_CONS_INDEX 2 296 #undef CONFIG_SERIAL_SOFTWARE_FIFO 297 #define CONFIG_SYS_NS16550 298 #define CONFIG_SYS_NS16550_SERIAL 299 #define CONFIG_SYS_NS16550_REG_SIZE 1 300 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 301 302 #define CONFIG_SYS_BAUDRATE_TABLE \ 303 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 304 305 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 306 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 307 308 /* Use the HUSH parser */ 309 #define CONFIG_SYS_HUSH_PARSER 310 #ifdef CONFIG_SYS_HUSH_PARSER 311 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 312 #endif 313 314 /* pass open firmware flat tree */ 315 #define CONFIG_OF_LIBFDT 1 316 #define CONFIG_OF_BOARD_SETUP 1 317 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 318 319 #define CONFIG_SYS_64BIT_VSPRINTF 1 320 #define CONFIG_SYS_64BIT_STRTOUL 1 321 322 /* 323 * I2C 324 */ 325 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 326 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 327 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 328 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 329 #define CONFIG_SYS_I2C_SLAVE 0x7F 330 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 331 #define CONFIG_SYS_I2C_OFFSET 0x3000 332 333 /* EEPROM */ 334 #define CONFIG_ID_EEPROM 335 #define CONFIG_SYS_I2C_EEPROM_CCID 336 #define CONFIG_SYS_ID_EEPROM 337 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 338 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 339 340 /* 341 * General PCI 342 * Memory space is mapped 1-1, but I/O space must start from 0. 343 */ 344 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 345 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 346 347 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 348 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 349 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 350 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 351 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 352 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 353 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 354 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 355 356 #ifdef CONFIG_PCI2 357 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 358 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 359 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 360 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 361 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 362 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 363 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 364 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 365 #endif 366 367 #ifdef CONFIG_PCIE1 368 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 369 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 370 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 371 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 372 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 373 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 374 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 375 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 376 #endif 377 378 #ifdef CONFIG_RIO 379 /* 380 * RapidIO MMU 381 */ 382 #define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 383 #define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 384 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 385 #endif 386 387 #ifdef CONFIG_LEGACY 388 #define BRIDGE_ID 17 389 #define VIA_ID 2 390 #else 391 #define BRIDGE_ID 28 392 #define VIA_ID 4 393 #endif 394 395 #if defined(CONFIG_PCI) 396 397 #define CONFIG_NET_MULTI 398 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 399 400 #undef CONFIG_EEPRO100 401 #undef CONFIG_TULIP 402 403 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 404 405 #endif /* CONFIG_PCI */ 406 407 408 #if defined(CONFIG_TSEC_ENET) 409 410 #ifndef CONFIG_NET_MULTI 411 #define CONFIG_NET_MULTI 1 412 #endif 413 414 #define CONFIG_MII 1 /* MII PHY management */ 415 #define CONFIG_TSEC1 1 416 #define CONFIG_TSEC1_NAME "eTSEC0" 417 #define CONFIG_TSEC2 1 418 #define CONFIG_TSEC2_NAME "eTSEC1" 419 #define CONFIG_TSEC3 1 420 #define CONFIG_TSEC3_NAME "eTSEC2" 421 #define CONFIG_TSEC4 422 #define CONFIG_TSEC4_NAME "eTSEC3" 423 #undef CONFIG_MPC85XX_FEC 424 425 #define TSEC1_PHY_ADDR 0 426 #define TSEC2_PHY_ADDR 1 427 #define TSEC3_PHY_ADDR 2 428 #define TSEC4_PHY_ADDR 3 429 430 #define TSEC1_PHYIDX 0 431 #define TSEC2_PHYIDX 0 432 #define TSEC3_PHYIDX 0 433 #define TSEC4_PHYIDX 0 434 #define TSEC1_FLAGS TSEC_GIGABIT 435 #define TSEC2_FLAGS TSEC_GIGABIT 436 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 437 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 438 439 /* Options are: eTSEC[0-3] */ 440 #define CONFIG_ETHPRIME "eTSEC0" 441 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 442 #endif /* CONFIG_TSEC_ENET */ 443 444 /* 445 * Environment 446 */ 447 #define CONFIG_ENV_IS_IN_FLASH 1 448 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 449 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 450 #define CONFIG_ENV_SIZE 0x2000 451 452 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 453 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 454 455 /* 456 * BOOTP options 457 */ 458 #define CONFIG_BOOTP_BOOTFILESIZE 459 #define CONFIG_BOOTP_BOOTPATH 460 #define CONFIG_BOOTP_GATEWAY 461 #define CONFIG_BOOTP_HOSTNAME 462 463 464 /* 465 * Command line configuration. 466 */ 467 #include <config_cmd_default.h> 468 469 #define CONFIG_CMD_PING 470 #define CONFIG_CMD_I2C 471 #define CONFIG_CMD_MII 472 #define CONFIG_CMD_ELF 473 #define CONFIG_CMD_IRQ 474 #define CONFIG_CMD_SETEXPR 475 476 #if defined(CONFIG_PCI) 477 #define CONFIG_CMD_PCI 478 #endif 479 480 481 #undef CONFIG_WATCHDOG /* watchdog disabled */ 482 483 /* 484 * Miscellaneous configurable options 485 */ 486 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 487 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 488 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 489 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 490 #if defined(CONFIG_CMD_KGDB) 491 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 492 #else 493 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 494 #endif 495 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 496 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 497 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 498 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 499 500 /* 501 * For booting Linux, the board info and command line data 502 * have to be in the first 16 MB of memory, since this is 503 * the maximum mapped by the Linux kernel during initialization. 504 */ 505 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 506 507 /* 508 * Internal Definitions 509 * 510 * Boot Flags 511 */ 512 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 513 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 514 515 #if defined(CONFIG_CMD_KGDB) 516 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 517 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 518 #endif 519 520 /* 521 * Environment Configuration 522 */ 523 524 /* The mac addresses for all ethernet interface */ 525 #if defined(CONFIG_TSEC_ENET) 526 #define CONFIG_HAS_ETH0 527 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 528 #define CONFIG_HAS_ETH1 529 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 530 #define CONFIG_HAS_ETH2 531 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 532 #define CONFIG_HAS_ETH3 533 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 534 #endif 535 536 #define CONFIG_IPADDR 192.168.1.253 537 538 #define CONFIG_HOSTNAME unknown 539 #define CONFIG_ROOTPATH /nfsroot 540 #define CONFIG_BOOTFILE 8548cds/uImage.uboot 541 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 542 543 #define CONFIG_SERVERIP 192.168.1.1 544 #define CONFIG_GATEWAYIP 192.168.1.1 545 #define CONFIG_NETMASK 255.255.255.0 546 547 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 548 549 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 550 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 551 552 #define CONFIG_BAUDRATE 115200 553 554 #define CONFIG_EXTRA_ENV_SETTINGS \ 555 "netdev=eth0\0" \ 556 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 557 "tftpflash=tftpboot $loadaddr $uboot; " \ 558 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 559 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 560 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 561 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 562 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 563 "consoledev=ttyS1\0" \ 564 "ramdiskaddr=2000000\0" \ 565 "ramdiskfile=ramdisk.uboot\0" \ 566 "fdtaddr=c00000\0" \ 567 "fdtfile=mpc8548cds.dtb\0" 568 569 #define CONFIG_NFSBOOTCOMMAND \ 570 "setenv bootargs root=/dev/nfs rw " \ 571 "nfsroot=$serverip:$rootpath " \ 572 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 573 "console=$consoledev,$baudrate $othbootargs;" \ 574 "tftp $loadaddr $bootfile;" \ 575 "tftp $fdtaddr $fdtfile;" \ 576 "bootm $loadaddr - $fdtaddr" 577 578 579 #define CONFIG_RAMBOOTCOMMAND \ 580 "setenv bootargs root=/dev/ram rw " \ 581 "console=$consoledev,$baudrate $othbootargs;" \ 582 "tftp $ramdiskaddr $ramdiskfile;" \ 583 "tftp $loadaddr $bootfile;" \ 584 "tftp $fdtaddr $fdtfile;" \ 585 "bootm $loadaddr $ramdiskaddr $fdtaddr" 586 587 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 588 589 #endif /* __CONFIG_H */ 590