1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #undef CONFIG_PCI 40 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 41 #define CONFIG_ENV_OVERWRITE 42 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 43 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 44 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 45 46 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 48 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 49 50 51 /* 52 * When initializing flash, if we cannot find the manufacturer ID, 53 * assume this is the AMD flash associated with the CDS board. 54 * This allows booting from a promjet. 55 */ 56 #define CONFIG_ASSUME_AMD_FLASH 57 58 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 59 60 #ifndef __ASSEMBLY__ 61 extern unsigned long get_clock_freq(void); 62 #endif 63 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 64 65 /* 66 * These can be toggled for performance analysis, otherwise use default. 67 */ 68 #define CONFIG_L2_CACHE /* toggle L2 cache */ 69 #define CONFIG_BTB /* toggle branch predition */ 70 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 71 72 /* 73 * Only possible on E500 Version 2 or newer cores. 74 */ 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 78 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 79 80 #undef CFG_DRAM_TEST /* memory test, takes time */ 81 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 82 #define CFG_MEMTEST_END 0x00400000 83 84 /* 85 * Base addresses -- Note these are effective addresses where the 86 * actual resources get mapped (not physical addresses) 87 */ 88 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 89 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 90 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 91 92 /* 93 * DDR Setup 94 */ 95 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 96 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 97 98 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 99 100 /* 101 * Make sure required options are set 102 */ 103 #ifndef CONFIG_SPD_EEPROM 104 #error ("CONFIG_SPD_EEPROM is required") 105 #endif 106 107 #undef CONFIG_CLOCKS_IN_MHZ 108 109 110 /* 111 * Local Bus Definitions 112 */ 113 114 /* 115 * FLASH on the Local Bus 116 * Two banks, 8M each, using the CFI driver. 117 * Boot from BR0/OR0 bank at 0xff00_0000 118 * Alternate BR1/OR1 bank at 0xff80_0000 119 * 120 * BR0, BR1: 121 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 122 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 123 * Port Size = 16 bits = BRx[19:20] = 10 124 * Use GPCM = BRx[24:26] = 000 125 * Valid = BRx[31] = 1 126 * 127 * 0 4 8 12 16 20 24 28 128 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 129 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 130 * 131 * OR0, OR1: 132 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 133 * Reserved ORx[17:18] = 11, confusion here? 134 * CSNT = ORx[20] = 1 135 * ACS = half cycle delay = ORx[21:22] = 11 136 * SCY = 6 = ORx[24:27] = 0110 137 * TRLX = use relaxed timing = ORx[29] = 1 138 * EAD = use external address latch delay = OR[31] = 1 139 * 140 * 0 4 8 12 16 20 24 28 141 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 142 */ 143 144 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 145 146 #define CFG_BR0_PRELIM 0xff801001 147 #define CFG_BR1_PRELIM 0xff001001 148 149 #define CFG_OR0_PRELIM 0xff806e65 150 #define CFG_OR1_PRELIM 0xff806e65 151 152 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} 153 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 154 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 155 #undef CFG_FLASH_CHECKSUM 156 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 157 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 158 159 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 160 161 #define CFG_FLASH_CFI_DRIVER 162 #define CFG_FLASH_CFI 163 #define CFG_FLASH_EMPTY_INFO 164 165 166 /* 167 * SDRAM on the Local Bus 168 */ 169 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 170 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 171 172 /* 173 * Base Register 2 and Option Register 2 configure SDRAM. 174 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 175 * 176 * For BR2, need: 177 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 178 * port-size = 32-bits = BR2[19:20] = 11 179 * no parity checking = BR2[21:22] = 00 180 * SDRAM for MSEL = BR2[24:26] = 011 181 * Valid = BR[31] = 1 182 * 183 * 0 4 8 12 16 20 24 28 184 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 185 * 186 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 187 * FIXME: the top 17 bits of BR2. 188 */ 189 190 #define CFG_BR2_PRELIM 0xf0001861 191 192 /* 193 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 194 * 195 * For OR2, need: 196 * 64MB mask for AM, OR2[0:7] = 1111 1100 197 * XAM, OR2[17:18] = 11 198 * 9 columns OR2[19-21] = 010 199 * 13 rows OR2[23-25] = 100 200 * EAD set for extra time OR[31] = 1 201 * 202 * 0 4 8 12 16 20 24 28 203 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 204 */ 205 206 #define CFG_OR2_PRELIM 0xfc006901 207 208 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 209 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 210 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 211 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 212 213 /* 214 * LSDMR masks 215 */ 216 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 217 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 218 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 219 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 220 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 221 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 222 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 223 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 224 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 225 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 226 227 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 230 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 231 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 232 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 233 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 234 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 235 236 /* 237 * Common settings for all Local Bus SDRAM commands. 238 * At run time, either BSMA1516 (for CPU 1.1) 239 * or BSMA1617 (for CPU 1.0) (old) 240 * is OR'ed in too. 241 */ 242 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 243 | CFG_LBC_LSDMR_PRETOACT7 \ 244 | CFG_LBC_LSDMR_ACTTORW7 \ 245 | CFG_LBC_LSDMR_BL8 \ 246 | CFG_LBC_LSDMR_WRC4 \ 247 | CFG_LBC_LSDMR_CL3 \ 248 | CFG_LBC_LSDMR_RFEN \ 249 ) 250 251 /* 252 * The CADMUS registers are connected to CS3 on CDS. 253 * The new memory map places CADMUS at 0xf8000000. 254 * 255 * For BR3, need: 256 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 257 * port-size = 8-bits = BR[19:20] = 01 258 * no parity checking = BR[21:22] = 00 259 * GPMC for MSEL = BR[24:26] = 000 260 * Valid = BR[31] = 1 261 * 262 * 0 4 8 12 16 20 24 28 263 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 264 * 265 * For OR3, need: 266 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 267 * disable buffer ctrl OR[19] = 0 268 * CSNT OR[20] = 1 269 * ACS OR[21:22] = 11 270 * XACS OR[23] = 1 271 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 272 * SETA OR[28] = 0 273 * TRLX OR[29] = 1 274 * EHTR OR[30] = 1 275 * EAD extra time OR[31] = 1 276 * 277 * 0 4 8 12 16 20 24 28 278 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 279 */ 280 281 #define CADMUS_BASE_ADDR 0xf8000000 282 #define CFG_BR3_PRELIM 0xf8000801 283 #define CFG_OR3_PRELIM 0xfff00ff7 284 285 #define CONFIG_L1_INIT_RAM 286 #define CFG_INIT_RAM_LOCK 1 287 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 288 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 289 290 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 291 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 292 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 293 294 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 295 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 296 297 /* Serial Port */ 298 #define CONFIG_CONS_INDEX 2 299 #undef CONFIG_SERIAL_SOFTWARE_FIFO 300 #define CFG_NS16550 301 #define CFG_NS16550_SERIAL 302 #define CFG_NS16550_REG_SIZE 1 303 #define CFG_NS16550_CLK get_bus_freq(0) 304 305 #define CFG_BAUDRATE_TABLE \ 306 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 307 308 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 309 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 310 311 /* Use the HUSH parser */ 312 #define CFG_HUSH_PARSER 313 #ifdef CFG_HUSH_PARSER 314 #define CFG_PROMPT_HUSH_PS2 "> " 315 #endif 316 317 /* pass open firmware flat tree */ 318 #define CONFIG_OF_FLAT_TREE 1 319 #define CONFIG_OF_BOARD_SETUP 1 320 321 /* maximum size of the flat tree (8K) */ 322 #define OF_FLAT_TREE_MAX_SIZE 8192 323 324 #define OF_CPU "PowerPC,8548@0" 325 #define OF_SOC "soc8548@e0000000" 326 #define OF_TBCLK (bd->bi_busfreq / 8) 327 #define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" 328 329 /* I2C */ 330 #define CONFIG_HARD_I2C /* I2C with hardware support */ 331 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 332 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 333 #define CFG_I2C_EEPROM_ADDR 0x57 334 #define CFG_I2C_SLAVE 0x7F 335 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 336 337 /* 338 * General PCI 339 * Addresses are mapped 1-1. 340 */ 341 #define CFG_PCI1_MEM_BASE 0x80000000 342 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 343 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 344 #define CFG_PCI1_IO_BASE 0x00000000 345 #define CFG_PCI1_IO_PHYS 0xe2000000 346 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 347 348 #define CFG_PCI2_MEM_BASE 0xa0000000 349 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 350 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 351 #define CFG_PCI2_IO_BASE 0x00000000 352 #define CFG_PCI2_IO_PHYS 0xe2100000 353 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 354 355 356 #if defined(CONFIG_PCI) 357 358 #define CONFIG_NET_MULTI 359 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 360 #define CONFIG_85XX_PCI2 361 362 #undef CONFIG_EEPRO100 363 #undef CONFIG_TULIP 364 365 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 366 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 367 368 #endif /* CONFIG_PCI */ 369 370 371 #if defined(CONFIG_TSEC_ENET) 372 373 #ifndef CONFIG_NET_MULTI 374 #define CONFIG_NET_MULTI 1 375 #endif 376 377 #define CONFIG_MII 1 /* MII PHY management */ 378 #define CONFIG_MPC85XX_TSEC1 1 379 #define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" 380 #define CONFIG_MPC85XX_TSEC2 1 381 #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" 382 #define CONFIG_MPC85XX_TSEC3 1 383 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" 384 #undef CONFIG_MPC85XX_TSEC4 385 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" 386 #undef CONFIG_MPC85XX_FEC 387 388 #define TSEC1_PHY_ADDR 0 389 #define TSEC2_PHY_ADDR 1 390 #define TSEC3_PHY_ADDR 2 391 #define TSEC4_PHY_ADDR 3 392 #define FEC_PHY_ADDR 3 393 394 #define TSEC1_PHYIDX 0 395 #define TSEC2_PHYIDX 0 396 #define TSEC3_PHYIDX 0 397 #define TSEC4_PHYIDX 0 398 #define FEC_PHYIDX 0 399 400 /* Options are: eTSEC[0-3] */ 401 #define CONFIG_ETHPRIME "eTSEC0" 402 403 #endif /* CONFIG_TSEC_ENET */ 404 405 /* 406 * Environment 407 */ 408 #define CFG_ENV_IS_IN_FLASH 1 409 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 410 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 411 #define CFG_ENV_SIZE 0x2000 412 413 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 414 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 415 416 #if defined(CONFIG_PCI) 417 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 418 | CFG_CMD_PCI \ 419 | CFG_CMD_PING \ 420 | CFG_CMD_I2C \ 421 | CFG_CMD_MII) 422 #else 423 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 424 | CFG_CMD_PING \ 425 | CFG_CMD_I2C \ 426 | CFG_CMD_MII) 427 #endif 428 #include <cmd_confdefs.h> 429 430 #undef CONFIG_WATCHDOG /* watchdog disabled */ 431 432 /* 433 * Miscellaneous configurable options 434 */ 435 #define CFG_LONGHELP /* undef to save memory */ 436 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 437 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 438 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 439 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 440 #else 441 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 442 #endif 443 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 444 #define CFG_MAXARGS 16 /* max number of command args */ 445 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 446 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 447 448 /* 449 * For booting Linux, the board info and command line data 450 * have to be in the first 8 MB of memory, since this is 451 * the maximum mapped by the Linux kernel during initialization. 452 */ 453 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 454 455 /* Cache Configuration */ 456 #define CFG_DCACHE_SIZE 32768 457 #define CFG_CACHELINE_SIZE 32 458 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 459 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 460 #endif 461 462 /* 463 * Internal Definitions 464 * 465 * Boot Flags 466 */ 467 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 468 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 469 470 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 471 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 472 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 473 #endif 474 475 /* 476 * Environment Configuration 477 */ 478 479 /* The mac addresses for all ethernet interface */ 480 #if defined(CONFIG_TSEC_ENET) 481 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 482 #define CONFIG_HAS_ETH1 483 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 484 #define CONFIG_HAS_ETH2 485 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 486 #endif 487 488 #define CONFIG_IPADDR 192.168.1.253 489 490 #define CONFIG_HOSTNAME unknown 491 #define CONFIG_ROOTPATH /nfsroot 492 #define CONFIG_BOOTFILE your.uImage 493 494 #define CONFIG_SERVERIP 192.168.1.1 495 #define CONFIG_GATEWAYIP 192.168.1.1 496 #define CONFIG_NETMASK 255.255.255.0 497 498 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 499 500 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 501 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 502 503 #define CONFIG_BAUDRATE 115200 504 505 #define CONFIG_EXTRA_ENV_SETTINGS \ 506 "netdev=eth0\0" \ 507 "consoledev=ttyS1\0" \ 508 "ramdiskaddr=400000\0" \ 509 "ramdiskfile=your.ramdisk.u-boot\0" 510 511 #define CONFIG_NFSBOOTCOMMAND \ 512 "setenv bootargs root=/dev/nfs rw " \ 513 "nfsroot=$serverip:$rootpath " \ 514 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 515 "console=$consoledev,$baudrate $othbootargs;" \ 516 "tftp $loadaddr $bootfile;" \ 517 "bootm $loadaddr" 518 519 #define CONFIG_RAMBOOTCOMMAND \ 520 "setenv bootargs root=/dev/ram rw " \ 521 "console=$consoledev,$baudrate $othbootargs;" \ 522 "tftp $ramdiskaddr $ramdiskfile;" \ 523 "tftp $loadaddr $bootfile;" \ 524 "bootm $loadaddr $ramdiskaddr" 525 526 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 527 528 #endif /* __CONFIG_H */ 529