1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 20 21 #ifndef CONFIG_SYS_TEXT_BASE 22 #define CONFIG_SYS_TEXT_BASE 0xfff80000 23 #endif 24 25 #define CONFIG_SYS_SRIO 26 #define CONFIG_SRIO1 /* SRIO port 1 */ 27 28 #define CONFIG_PCI1 /* PCI controller 1 */ 29 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 30 #undef CONFIG_PCI2 31 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 32 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 33 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 34 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 35 36 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 37 #define CONFIG_ENV_OVERWRITE 38 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 39 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 40 41 #define CONFIG_FSL_VIA 42 43 #ifndef __ASSEMBLY__ 44 extern unsigned long get_clock_freq(void); 45 #endif 46 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 47 48 /* 49 * These can be toggled for performance analysis, otherwise use default. 50 */ 51 #define CONFIG_L2_CACHE /* toggle L2 cache */ 52 #define CONFIG_BTB /* toggle branch predition */ 53 54 /* 55 * Only possible on E500 Version 2 or newer cores. 56 */ 57 #define CONFIG_ENABLE_36BIT_PHYS 1 58 59 #ifdef CONFIG_PHYS_64BIT 60 #define CONFIG_ADDR_MAP 61 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 62 #endif 63 64 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 65 #define CONFIG_SYS_MEMTEST_END 0x00400000 66 67 #define CONFIG_SYS_CCSRBAR 0xe0000000 68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 69 70 /* DDR Setup */ 71 #define CONFIG_SYS_FSL_DDR2 72 #undef CONFIG_FSL_DDR_INTERACTIVE 73 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 74 #define CONFIG_DDR_SPD 75 76 #define CONFIG_DDR_ECC 77 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 78 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 79 80 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 81 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 82 83 #define CONFIG_NUM_DDR_CONTROLLERS 1 84 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 85 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 86 87 /* I2C addresses of SPD EEPROMs */ 88 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 89 90 /* Make sure required options are set */ 91 #ifndef CONFIG_SPD_EEPROM 92 #error ("CONFIG_SPD_EEPROM is required") 93 #endif 94 95 #undef CONFIG_CLOCKS_IN_MHZ 96 /* 97 * Physical Address Map 98 * 99 * 32bit: 100 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 101 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 102 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 103 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 104 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 105 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 106 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 107 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 108 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 109 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 110 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 111 * 112 * 36bit: 113 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 114 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 115 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 116 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 117 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 118 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 119 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 120 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 121 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 122 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 123 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 124 * 125 */ 126 127 /* 128 * Local Bus Definitions 129 */ 130 131 /* 132 * FLASH on the Local Bus 133 * Two banks, 8M each, using the CFI driver. 134 * Boot from BR0/OR0 bank at 0xff00_0000 135 * Alternate BR1/OR1 bank at 0xff80_0000 136 * 137 * BR0, BR1: 138 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 139 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 140 * Port Size = 16 bits = BRx[19:20] = 10 141 * Use GPCM = BRx[24:26] = 000 142 * Valid = BRx[31] = 1 143 * 144 * 0 4 8 12 16 20 24 28 145 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 146 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 147 * 148 * OR0, OR1: 149 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 150 * Reserved ORx[17:18] = 11, confusion here? 151 * CSNT = ORx[20] = 1 152 * ACS = half cycle delay = ORx[21:22] = 11 153 * SCY = 6 = ORx[24:27] = 0110 154 * TRLX = use relaxed timing = ORx[29] = 1 155 * EAD = use external address latch delay = OR[31] = 1 156 * 157 * 0 4 8 12 16 20 24 28 158 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 159 */ 160 161 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 162 #ifdef CONFIG_PHYS_64BIT 163 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 164 #else 165 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 166 #endif 167 168 #define CONFIG_SYS_BR0_PRELIM \ 169 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 170 #define CONFIG_SYS_BR1_PRELIM \ 171 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 172 173 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 174 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 175 176 #define CONFIG_SYS_FLASH_BANKS_LIST \ 177 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 178 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 179 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 180 #undef CONFIG_SYS_FLASH_CHECKSUM 181 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 182 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 183 184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 185 186 #define CONFIG_FLASH_CFI_DRIVER 187 #define CONFIG_SYS_FLASH_CFI 188 #define CONFIG_SYS_FLASH_EMPTY_INFO 189 190 #define CONFIG_HWCONFIG /* enable hwconfig */ 191 192 /* 193 * SDRAM on the Local Bus 194 */ 195 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 196 #ifdef CONFIG_PHYS_64BIT 197 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 198 #else 199 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 200 #endif 201 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 202 203 /* 204 * Base Register 2 and Option Register 2 configure SDRAM. 205 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 206 * 207 * For BR2, need: 208 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 209 * port-size = 32-bits = BR2[19:20] = 11 210 * no parity checking = BR2[21:22] = 00 211 * SDRAM for MSEL = BR2[24:26] = 011 212 * Valid = BR[31] = 1 213 * 214 * 0 4 8 12 16 20 24 28 215 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 216 * 217 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 218 * FIXME: the top 17 bits of BR2. 219 */ 220 221 #define CONFIG_SYS_BR2_PRELIM \ 222 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 223 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 224 225 /* 226 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 227 * 228 * For OR2, need: 229 * 64MB mask for AM, OR2[0:7] = 1111 1100 230 * XAM, OR2[17:18] = 11 231 * 9 columns OR2[19-21] = 010 232 * 13 rows OR2[23-25] = 100 233 * EAD set for extra time OR[31] = 1 234 * 235 * 0 4 8 12 16 20 24 28 236 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 237 */ 238 239 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 240 241 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 242 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 243 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 244 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 245 246 /* 247 * Common settings for all Local Bus SDRAM commands. 248 * At run time, either BSMA1516 (for CPU 1.1) 249 * or BSMA1617 (for CPU 1.0) (old) 250 * is OR'ed in too. 251 */ 252 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 253 | LSDMR_PRETOACT7 \ 254 | LSDMR_ACTTORW7 \ 255 | LSDMR_BL8 \ 256 | LSDMR_WRC4 \ 257 | LSDMR_CL3 \ 258 | LSDMR_RFEN \ 259 ) 260 261 /* 262 * The CADMUS registers are connected to CS3 on CDS. 263 * The new memory map places CADMUS at 0xf8000000. 264 * 265 * For BR3, need: 266 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 267 * port-size = 8-bits = BR[19:20] = 01 268 * no parity checking = BR[21:22] = 00 269 * GPMC for MSEL = BR[24:26] = 000 270 * Valid = BR[31] = 1 271 * 272 * 0 4 8 12 16 20 24 28 273 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 274 * 275 * For OR3, need: 276 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 277 * disable buffer ctrl OR[19] = 0 278 * CSNT OR[20] = 1 279 * ACS OR[21:22] = 11 280 * XACS OR[23] = 1 281 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 282 * SETA OR[28] = 0 283 * TRLX OR[29] = 1 284 * EHTR OR[30] = 1 285 * EAD extra time OR[31] = 1 286 * 287 * 0 4 8 12 16 20 24 28 288 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 289 */ 290 291 #define CONFIG_FSL_CADMUS 292 293 #define CADMUS_BASE_ADDR 0xf8000000 294 #ifdef CONFIG_PHYS_64BIT 295 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 296 #else 297 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 298 #endif 299 #define CONFIG_SYS_BR3_PRELIM \ 300 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 301 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 302 303 #define CONFIG_SYS_INIT_RAM_LOCK 1 304 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 305 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 306 307 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 308 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 309 310 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 311 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 312 313 /* Serial Port */ 314 #define CONFIG_CONS_INDEX 2 315 #define CONFIG_SYS_NS16550_SERIAL 316 #define CONFIG_SYS_NS16550_REG_SIZE 1 317 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 318 319 #define CONFIG_SYS_BAUDRATE_TABLE \ 320 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 321 322 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 323 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 324 325 /* 326 * I2C 327 */ 328 #define CONFIG_SYS_I2C 329 #define CONFIG_SYS_I2C_FSL 330 #define CONFIG_SYS_FSL_I2C_SPEED 400000 331 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 332 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 333 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 334 335 /* EEPROM */ 336 #define CONFIG_ID_EEPROM 337 #define CONFIG_SYS_I2C_EEPROM_CCID 338 #define CONFIG_SYS_ID_EEPROM 339 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 340 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 341 342 /* 343 * General PCI 344 * Memory space is mapped 1-1, but I/O space must start from 0. 345 */ 346 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 347 #ifdef CONFIG_PHYS_64BIT 348 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 349 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 350 #else 351 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 352 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 353 #endif 354 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 355 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 356 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 357 #ifdef CONFIG_PHYS_64BIT 358 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 359 #else 360 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 361 #endif 362 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 363 364 #ifdef CONFIG_PCIE1 365 #define CONFIG_SYS_PCIE1_NAME "Slot" 366 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 367 #ifdef CONFIG_PHYS_64BIT 368 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 369 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 370 #else 371 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 372 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 373 #endif 374 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 375 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 376 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 377 #ifdef CONFIG_PHYS_64BIT 378 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 379 #else 380 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 381 #endif 382 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 383 #endif 384 385 /* 386 * RapidIO MMU 387 */ 388 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 389 #ifdef CONFIG_PHYS_64BIT 390 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 391 #else 392 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 393 #endif 394 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 395 396 #ifdef CONFIG_LEGACY 397 #define BRIDGE_ID 17 398 #define VIA_ID 2 399 #else 400 #define BRIDGE_ID 28 401 #define VIA_ID 4 402 #endif 403 404 #if defined(CONFIG_PCI) 405 #undef CONFIG_EEPRO100 406 #undef CONFIG_TULIP 407 408 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 409 410 #endif /* CONFIG_PCI */ 411 412 #if defined(CONFIG_TSEC_ENET) 413 414 #define CONFIG_MII 1 /* MII PHY management */ 415 #define CONFIG_TSEC1 1 416 #define CONFIG_TSEC1_NAME "eTSEC0" 417 #define CONFIG_TSEC2 1 418 #define CONFIG_TSEC2_NAME "eTSEC1" 419 #define CONFIG_TSEC3 1 420 #define CONFIG_TSEC3_NAME "eTSEC2" 421 #define CONFIG_TSEC4 422 #define CONFIG_TSEC4_NAME "eTSEC3" 423 #undef CONFIG_MPC85XX_FEC 424 425 #define CONFIG_PHY_MARVELL 426 427 #define TSEC1_PHY_ADDR 0 428 #define TSEC2_PHY_ADDR 1 429 #define TSEC3_PHY_ADDR 2 430 #define TSEC4_PHY_ADDR 3 431 432 #define TSEC1_PHYIDX 0 433 #define TSEC2_PHYIDX 0 434 #define TSEC3_PHYIDX 0 435 #define TSEC4_PHYIDX 0 436 #define TSEC1_FLAGS TSEC_GIGABIT 437 #define TSEC2_FLAGS TSEC_GIGABIT 438 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 439 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 440 441 /* Options are: eTSEC[0-3] */ 442 #define CONFIG_ETHPRIME "eTSEC0" 443 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 444 #endif /* CONFIG_TSEC_ENET */ 445 446 /* 447 * Environment 448 */ 449 #define CONFIG_ENV_IS_IN_FLASH 1 450 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 451 #define CONFIG_ENV_ADDR 0xfff80000 452 #else 453 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 454 #endif 455 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 456 #define CONFIG_ENV_SIZE 0x2000 457 458 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 459 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 460 461 /* 462 * BOOTP options 463 */ 464 #define CONFIG_BOOTP_BOOTFILESIZE 465 #define CONFIG_BOOTP_BOOTPATH 466 #define CONFIG_BOOTP_GATEWAY 467 #define CONFIG_BOOTP_HOSTNAME 468 469 /* 470 * Command line configuration. 471 */ 472 #define CONFIG_CMD_IRQ 473 #define CONFIG_CMD_REGINFO 474 475 #if defined(CONFIG_PCI) 476 #define CONFIG_CMD_PCI 477 #endif 478 479 #undef CONFIG_WATCHDOG /* watchdog disabled */ 480 481 /* 482 * Miscellaneous configurable options 483 */ 484 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 485 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 486 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 487 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 488 #if defined(CONFIG_CMD_KGDB) 489 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 490 #else 491 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 492 #endif 493 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 494 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 495 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 496 497 /* 498 * For booting Linux, the board info and command line data 499 * have to be in the first 64 MB of memory, since this is 500 * the maximum mapped by the Linux kernel during initialization. 501 */ 502 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 503 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 504 505 #if defined(CONFIG_CMD_KGDB) 506 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 507 #endif 508 509 /* 510 * Environment Configuration 511 */ 512 #if defined(CONFIG_TSEC_ENET) 513 #define CONFIG_HAS_ETH0 514 #define CONFIG_HAS_ETH1 515 #define CONFIG_HAS_ETH2 516 #define CONFIG_HAS_ETH3 517 #endif 518 519 #define CONFIG_IPADDR 192.168.1.253 520 521 #define CONFIG_HOSTNAME unknown 522 #define CONFIG_ROOTPATH "/nfsroot" 523 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 524 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 525 526 #define CONFIG_SERVERIP 192.168.1.1 527 #define CONFIG_GATEWAYIP 192.168.1.1 528 #define CONFIG_NETMASK 255.255.255.0 529 530 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 531 532 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 533 534 #define CONFIG_BAUDRATE 115200 535 536 #define CONFIG_EXTRA_ENV_SETTINGS \ 537 "hwconfig=fsl_ddr:ecc=off\0" \ 538 "netdev=eth0\0" \ 539 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 540 "tftpflash=tftpboot $loadaddr $uboot; " \ 541 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 542 " +$filesize; " \ 543 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 544 " +$filesize; " \ 545 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 546 " $filesize; " \ 547 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 548 " +$filesize; " \ 549 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 550 " $filesize\0" \ 551 "consoledev=ttyS1\0" \ 552 "ramdiskaddr=2000000\0" \ 553 "ramdiskfile=ramdisk.uboot\0" \ 554 "fdtaddr=1e00000\0" \ 555 "fdtfile=mpc8548cds.dtb\0" 556 557 #define CONFIG_NFSBOOTCOMMAND \ 558 "setenv bootargs root=/dev/nfs rw " \ 559 "nfsroot=$serverip:$rootpath " \ 560 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 561 "console=$consoledev,$baudrate $othbootargs;" \ 562 "tftp $loadaddr $bootfile;" \ 563 "tftp $fdtaddr $fdtfile;" \ 564 "bootm $loadaddr - $fdtaddr" 565 566 #define CONFIG_RAMBOOTCOMMAND \ 567 "setenv bootargs root=/dev/ram rw " \ 568 "console=$consoledev,$baudrate $othbootargs;" \ 569 "tftp $ramdiskaddr $ramdiskfile;" \ 570 "tftp $loadaddr $bootfile;" \ 571 "tftp $fdtaddr $fdtfile;" \ 572 "bootm $loadaddr $ramdiskaddr $fdtaddr" 573 574 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 575 576 #endif /* __CONFIG_H */ 577