1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #ifdef CONFIG_36BIT 17 #define CONFIG_PHYS_64BIT 18 #endif 19 20 /* High Level Configuration Options */ 21 #define CONFIG_BOOKE 1 /* BOOKE */ 22 #define CONFIG_E500 1 /* BOOKE e500 family */ 23 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 24 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 25 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 26 27 #ifndef CONFIG_SYS_TEXT_BASE 28 #define CONFIG_SYS_TEXT_BASE 0xfff80000 29 #endif 30 31 #define CONFIG_SYS_SRIO 32 #define CONFIG_SRIO1 /* SRIO port 1 */ 33 34 #define CONFIG_PCI /* enable any pci type devices */ 35 #define CONFIG_PCI1 /* PCI controller 1 */ 36 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 37 #undef CONFIG_PCI2 38 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 39 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 40 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 41 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 42 43 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 44 #define CONFIG_ENV_OVERWRITE 45 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 46 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 47 48 #define CONFIG_FSL_VIA 49 50 #ifndef __ASSEMBLY__ 51 extern unsigned long get_clock_freq(void); 52 #endif 53 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 54 55 /* 56 * These can be toggled for performance analysis, otherwise use default. 57 */ 58 #define CONFIG_L2_CACHE /* toggle L2 cache */ 59 #define CONFIG_BTB /* toggle branch predition */ 60 61 /* 62 * Only possible on E500 Version 2 or newer cores. 63 */ 64 #define CONFIG_ENABLE_36BIT_PHYS 1 65 66 #ifdef CONFIG_PHYS_64BIT 67 #define CONFIG_ADDR_MAP 68 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 69 #endif 70 71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 72 #define CONFIG_SYS_MEMTEST_END 0x00400000 73 74 #define CONFIG_SYS_CCSRBAR 0xe0000000 75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 76 77 /* DDR Setup */ 78 #define CONFIG_FSL_DDR2 79 #undef CONFIG_FSL_DDR_INTERACTIVE 80 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 81 #define CONFIG_DDR_SPD 82 83 #define CONFIG_DDR_ECC 84 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 85 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 86 87 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 88 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 89 90 #define CONFIG_NUM_DDR_CONTROLLERS 1 91 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 92 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 93 94 /* I2C addresses of SPD EEPROMs */ 95 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 96 97 /* Make sure required options are set */ 98 #ifndef CONFIG_SPD_EEPROM 99 #error ("CONFIG_SPD_EEPROM is required") 100 #endif 101 102 #undef CONFIG_CLOCKS_IN_MHZ 103 /* 104 * Physical Address Map 105 * 106 * 32bit: 107 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 108 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 109 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 110 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 111 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 112 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 113 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 114 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 115 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 116 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 117 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 118 * 119 * 36bit: 120 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 121 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 122 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 123 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 124 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 125 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 126 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 127 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 128 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 129 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 130 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 131 * 132 */ 133 134 135 /* 136 * Local Bus Definitions 137 */ 138 139 /* 140 * FLASH on the Local Bus 141 * Two banks, 8M each, using the CFI driver. 142 * Boot from BR0/OR0 bank at 0xff00_0000 143 * Alternate BR1/OR1 bank at 0xff80_0000 144 * 145 * BR0, BR1: 146 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 147 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 148 * Port Size = 16 bits = BRx[19:20] = 10 149 * Use GPCM = BRx[24:26] = 000 150 * Valid = BRx[31] = 1 151 * 152 * 0 4 8 12 16 20 24 28 153 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 154 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 155 * 156 * OR0, OR1: 157 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 158 * Reserved ORx[17:18] = 11, confusion here? 159 * CSNT = ORx[20] = 1 160 * ACS = half cycle delay = ORx[21:22] = 11 161 * SCY = 6 = ORx[24:27] = 0110 162 * TRLX = use relaxed timing = ORx[29] = 1 163 * EAD = use external address latch delay = OR[31] = 1 164 * 165 * 0 4 8 12 16 20 24 28 166 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 167 */ 168 169 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 170 #ifdef CONFIG_PHYS_64BIT 171 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 172 #else 173 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 174 #endif 175 176 #define CONFIG_SYS_BR0_PRELIM \ 177 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 178 #define CONFIG_SYS_BR1_PRELIM \ 179 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 180 181 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 182 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 183 184 #define CONFIG_SYS_FLASH_BANKS_LIST \ 185 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 186 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 187 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 188 #undef CONFIG_SYS_FLASH_CHECKSUM 189 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 190 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 191 192 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 193 194 #define CONFIG_FLASH_CFI_DRIVER 195 #define CONFIG_SYS_FLASH_CFI 196 #define CONFIG_SYS_FLASH_EMPTY_INFO 197 198 #define CONFIG_HWCONFIG /* enable hwconfig */ 199 200 /* 201 * SDRAM on the Local Bus 202 */ 203 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 204 #ifdef CONFIG_PHYS_64BIT 205 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 206 #else 207 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 208 #endif 209 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 210 211 /* 212 * Base Register 2 and Option Register 2 configure SDRAM. 213 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 214 * 215 * For BR2, need: 216 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 217 * port-size = 32-bits = BR2[19:20] = 11 218 * no parity checking = BR2[21:22] = 00 219 * SDRAM for MSEL = BR2[24:26] = 011 220 * Valid = BR[31] = 1 221 * 222 * 0 4 8 12 16 20 24 28 223 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 224 * 225 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 226 * FIXME: the top 17 bits of BR2. 227 */ 228 229 #define CONFIG_SYS_BR2_PRELIM \ 230 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 231 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 232 233 /* 234 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 235 * 236 * For OR2, need: 237 * 64MB mask for AM, OR2[0:7] = 1111 1100 238 * XAM, OR2[17:18] = 11 239 * 9 columns OR2[19-21] = 010 240 * 13 rows OR2[23-25] = 100 241 * EAD set for extra time OR[31] = 1 242 * 243 * 0 4 8 12 16 20 24 28 244 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 245 */ 246 247 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 248 249 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 250 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 251 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 252 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 253 254 /* 255 * Common settings for all Local Bus SDRAM commands. 256 * At run time, either BSMA1516 (for CPU 1.1) 257 * or BSMA1617 (for CPU 1.0) (old) 258 * is OR'ed in too. 259 */ 260 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 261 | LSDMR_PRETOACT7 \ 262 | LSDMR_ACTTORW7 \ 263 | LSDMR_BL8 \ 264 | LSDMR_WRC4 \ 265 | LSDMR_CL3 \ 266 | LSDMR_RFEN \ 267 ) 268 269 /* 270 * The CADMUS registers are connected to CS3 on CDS. 271 * The new memory map places CADMUS at 0xf8000000. 272 * 273 * For BR3, need: 274 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 275 * port-size = 8-bits = BR[19:20] = 01 276 * no parity checking = BR[21:22] = 00 277 * GPMC for MSEL = BR[24:26] = 000 278 * Valid = BR[31] = 1 279 * 280 * 0 4 8 12 16 20 24 28 281 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 282 * 283 * For OR3, need: 284 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 285 * disable buffer ctrl OR[19] = 0 286 * CSNT OR[20] = 1 287 * ACS OR[21:22] = 11 288 * XACS OR[23] = 1 289 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 290 * SETA OR[28] = 0 291 * TRLX OR[29] = 1 292 * EHTR OR[30] = 1 293 * EAD extra time OR[31] = 1 294 * 295 * 0 4 8 12 16 20 24 28 296 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 297 */ 298 299 #define CONFIG_FSL_CADMUS 300 301 #define CADMUS_BASE_ADDR 0xf8000000 302 #ifdef CONFIG_PHYS_64BIT 303 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 304 #else 305 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 306 #endif 307 #define CONFIG_SYS_BR3_PRELIM \ 308 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 309 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 310 311 #define CONFIG_SYS_INIT_RAM_LOCK 1 312 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 313 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 314 315 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 316 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 317 318 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 319 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 320 321 /* Serial Port */ 322 #define CONFIG_CONS_INDEX 2 323 #define CONFIG_SYS_NS16550 324 #define CONFIG_SYS_NS16550_SERIAL 325 #define CONFIG_SYS_NS16550_REG_SIZE 1 326 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 327 328 #define CONFIG_SYS_BAUDRATE_TABLE \ 329 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 330 331 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 332 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 333 334 /* Use the HUSH parser */ 335 #define CONFIG_SYS_HUSH_PARSER 336 337 /* pass open firmware flat tree */ 338 #define CONFIG_OF_LIBFDT 1 339 #define CONFIG_OF_BOARD_SETUP 1 340 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 341 342 /* 343 * I2C 344 */ 345 #define CONFIG_SYS_I2C 346 #define CONFIG_SYS_I2C_FSL 347 #define CONFIG_SYS_FSL_I2C_SPEED 400000 348 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 349 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 350 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 351 352 /* EEPROM */ 353 #define CONFIG_ID_EEPROM 354 #define CONFIG_SYS_I2C_EEPROM_CCID 355 #define CONFIG_SYS_ID_EEPROM 356 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 357 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 358 359 /* 360 * General PCI 361 * Memory space is mapped 1-1, but I/O space must start from 0. 362 */ 363 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 364 #ifdef CONFIG_PHYS_64BIT 365 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 366 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 367 #else 368 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 369 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 370 #endif 371 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 372 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 373 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 374 #ifdef CONFIG_PHYS_64BIT 375 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 376 #else 377 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 378 #endif 379 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 380 381 #ifdef CONFIG_PCIE1 382 #define CONFIG_SYS_PCIE1_NAME "Slot" 383 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 384 #ifdef CONFIG_PHYS_64BIT 385 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 386 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 387 #else 388 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 389 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 390 #endif 391 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 392 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 393 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 394 #ifdef CONFIG_PHYS_64BIT 395 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 396 #else 397 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 398 #endif 399 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 400 #endif 401 402 /* 403 * RapidIO MMU 404 */ 405 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 406 #ifdef CONFIG_PHYS_64BIT 407 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 408 #else 409 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 410 #endif 411 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 412 413 #ifdef CONFIG_LEGACY 414 #define BRIDGE_ID 17 415 #define VIA_ID 2 416 #else 417 #define BRIDGE_ID 28 418 #define VIA_ID 4 419 #endif 420 421 #if defined(CONFIG_PCI) 422 423 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 424 425 #undef CONFIG_EEPRO100 426 #undef CONFIG_TULIP 427 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 428 429 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 430 431 #endif /* CONFIG_PCI */ 432 433 434 #if defined(CONFIG_TSEC_ENET) 435 436 #define CONFIG_MII 1 /* MII PHY management */ 437 #define CONFIG_TSEC1 1 438 #define CONFIG_TSEC1_NAME "eTSEC0" 439 #define CONFIG_TSEC2 1 440 #define CONFIG_TSEC2_NAME "eTSEC1" 441 #define CONFIG_TSEC3 1 442 #define CONFIG_TSEC3_NAME "eTSEC2" 443 #define CONFIG_TSEC4 444 #define CONFIG_TSEC4_NAME "eTSEC3" 445 #undef CONFIG_MPC85XX_FEC 446 447 #define CONFIG_PHY_MARVELL 448 449 #define TSEC1_PHY_ADDR 0 450 #define TSEC2_PHY_ADDR 1 451 #define TSEC3_PHY_ADDR 2 452 #define TSEC4_PHY_ADDR 3 453 454 #define TSEC1_PHYIDX 0 455 #define TSEC2_PHYIDX 0 456 #define TSEC3_PHYIDX 0 457 #define TSEC4_PHYIDX 0 458 #define TSEC1_FLAGS TSEC_GIGABIT 459 #define TSEC2_FLAGS TSEC_GIGABIT 460 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 461 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 462 463 /* Options are: eTSEC[0-3] */ 464 #define CONFIG_ETHPRIME "eTSEC0" 465 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 466 #endif /* CONFIG_TSEC_ENET */ 467 468 /* 469 * Environment 470 */ 471 #define CONFIG_ENV_IS_IN_FLASH 1 472 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 473 #define CONFIG_ENV_ADDR 0xfff80000 474 #else 475 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 476 #endif 477 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 478 #define CONFIG_ENV_SIZE 0x2000 479 480 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 481 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 482 483 /* 484 * BOOTP options 485 */ 486 #define CONFIG_BOOTP_BOOTFILESIZE 487 #define CONFIG_BOOTP_BOOTPATH 488 #define CONFIG_BOOTP_GATEWAY 489 #define CONFIG_BOOTP_HOSTNAME 490 491 492 /* 493 * Command line configuration. 494 */ 495 #include <config_cmd_default.h> 496 497 #define CONFIG_CMD_PING 498 #define CONFIG_CMD_I2C 499 #define CONFIG_CMD_MII 500 #define CONFIG_CMD_ELF 501 #define CONFIG_CMD_IRQ 502 #define CONFIG_CMD_SETEXPR 503 #define CONFIG_CMD_REGINFO 504 505 #if defined(CONFIG_PCI) 506 #define CONFIG_CMD_PCI 507 #endif 508 509 510 #undef CONFIG_WATCHDOG /* watchdog disabled */ 511 512 /* 513 * Miscellaneous configurable options 514 */ 515 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 516 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 517 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 518 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 519 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 520 #if defined(CONFIG_CMD_KGDB) 521 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 522 #else 523 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 524 #endif 525 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 526 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 527 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 528 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 529 530 /* 531 * For booting Linux, the board info and command line data 532 * have to be in the first 64 MB of memory, since this is 533 * the maximum mapped by the Linux kernel during initialization. 534 */ 535 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 536 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 537 538 #if defined(CONFIG_CMD_KGDB) 539 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 540 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 541 #endif 542 543 /* 544 * Environment Configuration 545 */ 546 547 /* The mac addresses for all ethernet interface */ 548 #if defined(CONFIG_TSEC_ENET) 549 #define CONFIG_HAS_ETH0 550 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 551 #define CONFIG_HAS_ETH1 552 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 553 #define CONFIG_HAS_ETH2 554 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 555 #define CONFIG_HAS_ETH3 556 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 557 #endif 558 559 #define CONFIG_IPADDR 192.168.1.253 560 561 #define CONFIG_HOSTNAME unknown 562 #define CONFIG_ROOTPATH "/nfsroot" 563 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 564 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 565 566 #define CONFIG_SERVERIP 192.168.1.1 567 #define CONFIG_GATEWAYIP 192.168.1.1 568 #define CONFIG_NETMASK 255.255.255.0 569 570 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 571 572 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 573 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 574 575 #define CONFIG_BAUDRATE 115200 576 577 #define CONFIG_EXTRA_ENV_SETTINGS \ 578 "hwconfig=fsl_ddr:ecc=off\0" \ 579 "netdev=eth0\0" \ 580 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 581 "tftpflash=tftpboot $loadaddr $uboot; " \ 582 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 583 " +$filesize; " \ 584 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 585 " +$filesize; " \ 586 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 587 " $filesize; " \ 588 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 589 " +$filesize; " \ 590 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 591 " $filesize\0" \ 592 "consoledev=ttyS1\0" \ 593 "ramdiskaddr=2000000\0" \ 594 "ramdiskfile=ramdisk.uboot\0" \ 595 "fdtaddr=c00000\0" \ 596 "fdtfile=mpc8548cds.dtb\0" 597 598 #define CONFIG_NFSBOOTCOMMAND \ 599 "setenv bootargs root=/dev/nfs rw " \ 600 "nfsroot=$serverip:$rootpath " \ 601 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 602 "console=$consoledev,$baudrate $othbootargs;" \ 603 "tftp $loadaddr $bootfile;" \ 604 "tftp $fdtaddr $fdtfile;" \ 605 "bootm $loadaddr - $fdtaddr" 606 607 608 #define CONFIG_RAMBOOTCOMMAND \ 609 "setenv bootargs root=/dev/ram rw " \ 610 "console=$consoledev,$baudrate $othbootargs;" \ 611 "tftp $ramdiskaddr $ramdiskfile;" \ 612 "tftp $loadaddr $bootfile;" \ 613 "tftp $fdtaddr $fdtfile;" \ 614 "bootm $loadaddr $ramdiskaddr $fdtaddr" 615 616 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 617 618 #endif /* __CONFIG_H */ 619