1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 20 #ifndef CONFIG_SYS_TEXT_BASE 21 #define CONFIG_SYS_TEXT_BASE 0xfff80000 22 #endif 23 24 #define CONFIG_SYS_SRIO 25 #define CONFIG_SRIO1 /* SRIO port 1 */ 26 27 #define CONFIG_PCI1 /* PCI controller 1 */ 28 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 29 #undef CONFIG_PCI2 30 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 32 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 34 35 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 36 #define CONFIG_ENV_OVERWRITE 37 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 38 39 #define CONFIG_FSL_VIA 40 41 #ifndef __ASSEMBLY__ 42 extern unsigned long get_clock_freq(void); 43 #endif 44 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 45 46 /* 47 * These can be toggled for performance analysis, otherwise use default. 48 */ 49 #define CONFIG_L2_CACHE /* toggle L2 cache */ 50 #define CONFIG_BTB /* toggle branch predition */ 51 52 /* 53 * Only possible on E500 Version 2 or newer cores. 54 */ 55 #define CONFIG_ENABLE_36BIT_PHYS 1 56 57 #ifdef CONFIG_PHYS_64BIT 58 #define CONFIG_ADDR_MAP 59 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 60 #endif 61 62 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 63 #define CONFIG_SYS_MEMTEST_END 0x00400000 64 65 #define CONFIG_SYS_CCSRBAR 0xe0000000 66 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 67 68 /* DDR Setup */ 69 #define CONFIG_SYS_FSL_DDR2 70 #undef CONFIG_FSL_DDR_INTERACTIVE 71 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 72 #define CONFIG_DDR_SPD 73 74 #define CONFIG_DDR_ECC 75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 76 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 77 78 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 79 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 80 81 #define CONFIG_NUM_DDR_CONTROLLERS 1 82 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 83 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 84 85 /* I2C addresses of SPD EEPROMs */ 86 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 87 88 /* Make sure required options are set */ 89 #ifndef CONFIG_SPD_EEPROM 90 #error ("CONFIG_SPD_EEPROM is required") 91 #endif 92 93 #undef CONFIG_CLOCKS_IN_MHZ 94 /* 95 * Physical Address Map 96 * 97 * 32bit: 98 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 99 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 100 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 101 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 102 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 103 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 104 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 105 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 106 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 107 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 108 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 109 * 110 * 36bit: 111 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 112 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 113 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 114 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 115 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 116 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 117 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 118 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 119 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 120 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 121 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 122 * 123 */ 124 125 /* 126 * Local Bus Definitions 127 */ 128 129 /* 130 * FLASH on the Local Bus 131 * Two banks, 8M each, using the CFI driver. 132 * Boot from BR0/OR0 bank at 0xff00_0000 133 * Alternate BR1/OR1 bank at 0xff80_0000 134 * 135 * BR0, BR1: 136 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 137 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 138 * Port Size = 16 bits = BRx[19:20] = 10 139 * Use GPCM = BRx[24:26] = 000 140 * Valid = BRx[31] = 1 141 * 142 * 0 4 8 12 16 20 24 28 143 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 144 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 145 * 146 * OR0, OR1: 147 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 148 * Reserved ORx[17:18] = 11, confusion here? 149 * CSNT = ORx[20] = 1 150 * ACS = half cycle delay = ORx[21:22] = 11 151 * SCY = 6 = ORx[24:27] = 0110 152 * TRLX = use relaxed timing = ORx[29] = 1 153 * EAD = use external address latch delay = OR[31] = 1 154 * 155 * 0 4 8 12 16 20 24 28 156 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 157 */ 158 159 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 160 #ifdef CONFIG_PHYS_64BIT 161 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 162 #else 163 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 164 #endif 165 166 #define CONFIG_SYS_BR0_PRELIM \ 167 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 168 #define CONFIG_SYS_BR1_PRELIM \ 169 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 170 171 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 172 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 173 174 #define CONFIG_SYS_FLASH_BANKS_LIST \ 175 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 176 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 177 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 178 #undef CONFIG_SYS_FLASH_CHECKSUM 179 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 180 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 181 182 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 183 184 #define CONFIG_FLASH_CFI_DRIVER 185 #define CONFIG_SYS_FLASH_CFI 186 #define CONFIG_SYS_FLASH_EMPTY_INFO 187 188 #define CONFIG_HWCONFIG /* enable hwconfig */ 189 190 /* 191 * SDRAM on the Local Bus 192 */ 193 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 194 #ifdef CONFIG_PHYS_64BIT 195 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 196 #else 197 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 198 #endif 199 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 200 201 /* 202 * Base Register 2 and Option Register 2 configure SDRAM. 203 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 204 * 205 * For BR2, need: 206 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 207 * port-size = 32-bits = BR2[19:20] = 11 208 * no parity checking = BR2[21:22] = 00 209 * SDRAM for MSEL = BR2[24:26] = 011 210 * Valid = BR[31] = 1 211 * 212 * 0 4 8 12 16 20 24 28 213 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 214 * 215 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 216 * FIXME: the top 17 bits of BR2. 217 */ 218 219 #define CONFIG_SYS_BR2_PRELIM \ 220 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 221 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 222 223 /* 224 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 225 * 226 * For OR2, need: 227 * 64MB mask for AM, OR2[0:7] = 1111 1100 228 * XAM, OR2[17:18] = 11 229 * 9 columns OR2[19-21] = 010 230 * 13 rows OR2[23-25] = 100 231 * EAD set for extra time OR[31] = 1 232 * 233 * 0 4 8 12 16 20 24 28 234 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 235 */ 236 237 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 238 239 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 240 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 241 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 242 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 243 244 /* 245 * Common settings for all Local Bus SDRAM commands. 246 * At run time, either BSMA1516 (for CPU 1.1) 247 * or BSMA1617 (for CPU 1.0) (old) 248 * is OR'ed in too. 249 */ 250 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 251 | LSDMR_PRETOACT7 \ 252 | LSDMR_ACTTORW7 \ 253 | LSDMR_BL8 \ 254 | LSDMR_WRC4 \ 255 | LSDMR_CL3 \ 256 | LSDMR_RFEN \ 257 ) 258 259 /* 260 * The CADMUS registers are connected to CS3 on CDS. 261 * The new memory map places CADMUS at 0xf8000000. 262 * 263 * For BR3, need: 264 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 265 * port-size = 8-bits = BR[19:20] = 01 266 * no parity checking = BR[21:22] = 00 267 * GPMC for MSEL = BR[24:26] = 000 268 * Valid = BR[31] = 1 269 * 270 * 0 4 8 12 16 20 24 28 271 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 272 * 273 * For OR3, need: 274 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 275 * disable buffer ctrl OR[19] = 0 276 * CSNT OR[20] = 1 277 * ACS OR[21:22] = 11 278 * XACS OR[23] = 1 279 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 280 * SETA OR[28] = 0 281 * TRLX OR[29] = 1 282 * EHTR OR[30] = 1 283 * EAD extra time OR[31] = 1 284 * 285 * 0 4 8 12 16 20 24 28 286 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 287 */ 288 289 #define CONFIG_FSL_CADMUS 290 291 #define CADMUS_BASE_ADDR 0xf8000000 292 #ifdef CONFIG_PHYS_64BIT 293 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 294 #else 295 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 296 #endif 297 #define CONFIG_SYS_BR3_PRELIM \ 298 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 299 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 300 301 #define CONFIG_SYS_INIT_RAM_LOCK 1 302 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 303 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 304 305 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 306 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 307 308 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 309 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 310 311 /* Serial Port */ 312 #define CONFIG_CONS_INDEX 2 313 #define CONFIG_SYS_NS16550_SERIAL 314 #define CONFIG_SYS_NS16550_REG_SIZE 1 315 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 316 317 #define CONFIG_SYS_BAUDRATE_TABLE \ 318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 319 320 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 321 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 322 323 /* 324 * I2C 325 */ 326 #define CONFIG_SYS_I2C 327 #define CONFIG_SYS_I2C_FSL 328 #define CONFIG_SYS_FSL_I2C_SPEED 400000 329 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 330 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 331 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 332 333 /* EEPROM */ 334 #define CONFIG_ID_EEPROM 335 #define CONFIG_SYS_I2C_EEPROM_CCID 336 #define CONFIG_SYS_ID_EEPROM 337 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 338 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 339 340 /* 341 * General PCI 342 * Memory space is mapped 1-1, but I/O space must start from 0. 343 */ 344 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 345 #ifdef CONFIG_PHYS_64BIT 346 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 347 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 348 #else 349 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 350 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 351 #endif 352 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 353 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 354 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 355 #ifdef CONFIG_PHYS_64BIT 356 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 357 #else 358 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 359 #endif 360 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 361 362 #ifdef CONFIG_PCIE1 363 #define CONFIG_SYS_PCIE1_NAME "Slot" 364 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 365 #ifdef CONFIG_PHYS_64BIT 366 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 367 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 368 #else 369 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 370 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 371 #endif 372 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 373 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 374 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 375 #ifdef CONFIG_PHYS_64BIT 376 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 377 #else 378 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 379 #endif 380 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 381 #endif 382 383 /* 384 * RapidIO MMU 385 */ 386 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 387 #ifdef CONFIG_PHYS_64BIT 388 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 389 #else 390 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 391 #endif 392 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 393 394 #ifdef CONFIG_LEGACY 395 #define BRIDGE_ID 17 396 #define VIA_ID 2 397 #else 398 #define BRIDGE_ID 28 399 #define VIA_ID 4 400 #endif 401 402 #if defined(CONFIG_PCI) 403 #undef CONFIG_EEPRO100 404 #undef CONFIG_TULIP 405 406 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 407 408 #endif /* CONFIG_PCI */ 409 410 #if defined(CONFIG_TSEC_ENET) 411 412 #define CONFIG_MII 1 /* MII PHY management */ 413 #define CONFIG_TSEC1 1 414 #define CONFIG_TSEC1_NAME "eTSEC0" 415 #define CONFIG_TSEC2 1 416 #define CONFIG_TSEC2_NAME "eTSEC1" 417 #define CONFIG_TSEC3 1 418 #define CONFIG_TSEC3_NAME "eTSEC2" 419 #define CONFIG_TSEC4 420 #define CONFIG_TSEC4_NAME "eTSEC3" 421 #undef CONFIG_MPC85XX_FEC 422 423 #define CONFIG_PHY_MARVELL 424 425 #define TSEC1_PHY_ADDR 0 426 #define TSEC2_PHY_ADDR 1 427 #define TSEC3_PHY_ADDR 2 428 #define TSEC4_PHY_ADDR 3 429 430 #define TSEC1_PHYIDX 0 431 #define TSEC2_PHYIDX 0 432 #define TSEC3_PHYIDX 0 433 #define TSEC4_PHYIDX 0 434 #define TSEC1_FLAGS TSEC_GIGABIT 435 #define TSEC2_FLAGS TSEC_GIGABIT 436 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 437 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 438 439 /* Options are: eTSEC[0-3] */ 440 #define CONFIG_ETHPRIME "eTSEC0" 441 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 442 #endif /* CONFIG_TSEC_ENET */ 443 444 /* 445 * Environment 446 */ 447 #define CONFIG_ENV_IS_IN_FLASH 1 448 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 449 #define CONFIG_ENV_ADDR 0xfff80000 450 #else 451 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 452 #endif 453 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 454 #define CONFIG_ENV_SIZE 0x2000 455 456 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 457 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 458 459 /* 460 * BOOTP options 461 */ 462 #define CONFIG_BOOTP_BOOTFILESIZE 463 #define CONFIG_BOOTP_BOOTPATH 464 #define CONFIG_BOOTP_GATEWAY 465 #define CONFIG_BOOTP_HOSTNAME 466 467 /* 468 * Command line configuration. 469 */ 470 #define CONFIG_CMD_IRQ 471 #define CONFIG_CMD_REGINFO 472 473 #if defined(CONFIG_PCI) 474 #define CONFIG_CMD_PCI 475 #endif 476 477 #undef CONFIG_WATCHDOG /* watchdog disabled */ 478 479 /* 480 * Miscellaneous configurable options 481 */ 482 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 483 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 484 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 485 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 486 #if defined(CONFIG_CMD_KGDB) 487 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 488 #else 489 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 490 #endif 491 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 492 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 493 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 494 495 /* 496 * For booting Linux, the board info and command line data 497 * have to be in the first 64 MB of memory, since this is 498 * the maximum mapped by the Linux kernel during initialization. 499 */ 500 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 501 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 502 503 #if defined(CONFIG_CMD_KGDB) 504 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 505 #endif 506 507 /* 508 * Environment Configuration 509 */ 510 #if defined(CONFIG_TSEC_ENET) 511 #define CONFIG_HAS_ETH0 512 #define CONFIG_HAS_ETH1 513 #define CONFIG_HAS_ETH2 514 #define CONFIG_HAS_ETH3 515 #endif 516 517 #define CONFIG_IPADDR 192.168.1.253 518 519 #define CONFIG_HOSTNAME unknown 520 #define CONFIG_ROOTPATH "/nfsroot" 521 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 522 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 523 524 #define CONFIG_SERVERIP 192.168.1.1 525 #define CONFIG_GATEWAYIP 192.168.1.1 526 #define CONFIG_NETMASK 255.255.255.0 527 528 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 529 530 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 531 532 #define CONFIG_BAUDRATE 115200 533 534 #define CONFIG_EXTRA_ENV_SETTINGS \ 535 "hwconfig=fsl_ddr:ecc=off\0" \ 536 "netdev=eth0\0" \ 537 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 538 "tftpflash=tftpboot $loadaddr $uboot; " \ 539 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 540 " +$filesize; " \ 541 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 542 " +$filesize; " \ 543 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 544 " $filesize; " \ 545 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 546 " +$filesize; " \ 547 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 548 " $filesize\0" \ 549 "consoledev=ttyS1\0" \ 550 "ramdiskaddr=2000000\0" \ 551 "ramdiskfile=ramdisk.uboot\0" \ 552 "fdtaddr=1e00000\0" \ 553 "fdtfile=mpc8548cds.dtb\0" 554 555 #define CONFIG_NFSBOOTCOMMAND \ 556 "setenv bootargs root=/dev/nfs rw " \ 557 "nfsroot=$serverip:$rootpath " \ 558 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 559 "console=$consoledev,$baudrate $othbootargs;" \ 560 "tftp $loadaddr $bootfile;" \ 561 "tftp $fdtaddr $fdtfile;" \ 562 "bootm $loadaddr - $fdtaddr" 563 564 #define CONFIG_RAMBOOTCOMMAND \ 565 "setenv bootargs root=/dev/ram rw " \ 566 "console=$consoledev,$baudrate $othbootargs;" \ 567 "tftp $ramdiskaddr $ramdiskfile;" \ 568 "tftp $loadaddr $bootfile;" \ 569 "tftp $fdtaddr $fdtfile;" \ 570 "bootm $loadaddr $ramdiskaddr $fdtaddr" 571 572 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 573 574 #endif /* __CONFIG_H */ 575