1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8544ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8544 1 35 #define CONFIG_MPC8544DS 1 36 37 #undef CONFIG_PCI /* Enable PCI/PCIE */ 38 #undef CONFIG_PCI1 /* PCI controller 1 */ 39 #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 40 #undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 41 #undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ 42 #undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 43 44 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 45 #define CONFIG_ENV_OVERWRITE 46 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 47 #undef CONFIG_DDR_DLL 48 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 49 50 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 53 54 #define CONFIG_DDR_ECC_CMD 55 56 /* 57 * When initializing flash, if we cannot find the manufacturer ID, 58 * assume this is the AMD flash associated with the CDS board. 59 * This allows booting from a promjet. 60 */ 61 #define CONFIG_ASSUME_AMD_FLASH 62 63 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 64 65 #ifndef __ASSEMBLY__ 66 extern unsigned long get_board_sys_clk(unsigned long dummy); 67 #endif 68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 69 70 /* 71 * These can be toggled for performance analysis, otherwise use default. 72 */ 73 #define CONFIG_L2_CACHE /* toggle L2 cache */ 74 #define CONFIG_BTB /* toggle branch predition */ 75 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 76 #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ 77 78 /* 79 * Only possible on E500 Version 2 or newer cores. 80 */ 81 #define CONFIG_ENABLE_36BIT_PHYS 1 82 83 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 84 85 #undef CFG_DRAM_TEST /* memory test, takes time */ 86 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 87 #define CFG_MEMTEST_END 0x00400000 88 #define CFG_ALT_MEMTEST 89 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 90 91 /* 92 * Base addresses -- Note these are effective addresses where the 93 * actual resources get mapped (not physical addresses) 94 */ 95 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 96 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 97 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 98 99 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 100 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 101 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) 102 #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) 103 104 /* 105 * DDR Setup 106 */ 107 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 108 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 109 110 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 111 112 /* 113 * Make sure required options are set 114 */ 115 #ifndef CONFIG_SPD_EEPROM 116 #error ("CONFIG_SPD_EEPROM is required") 117 #endif 118 119 #undef CONFIG_CLOCKS_IN_MHZ 120 121 /* 122 * Memory map 123 * 124 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 125 * 126 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 127 * 128 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 129 * 130 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 131 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 132 * 133 * Localbus cacheable 134 * 135 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 136 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 137 * 138 * Localbus non-cacheable 139 * 140 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 141 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 142 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 143 * 144 */ 145 146 /* 147 * Local Bus Definitions 148 */ 149 #define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */ 150 151 #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 152 153 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 154 155 #define CFG_BR0_PRELIM 0xff801001 156 #define CFG_BR1_PRELIM 0xfe801001 157 158 #define CFG_OR0_PRELIM 0xff806e65 159 #define CFG_OR1_PRELIM 0xff806e65 160 161 #define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE} 162 163 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 164 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 165 #undef CFG_FLASH_CHECKSUM 166 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 167 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 168 169 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 170 171 #define CFG_FLASH_CFI_DRIVER 172 #define CFG_FLASH_CFI 173 #define CFG_FLASH_EMPTY_INFO 174 175 #define CFG_LBC_NONCACHE_BASE 0xf8000000 176 177 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ 178 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 179 180 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ 181 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 182 183 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 184 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 185 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 186 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 187 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 188 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 189 * register */ 190 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 191 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 192 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 193 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 194 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 195 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 196 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 197 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 198 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 199 200 201 /* define to use L1 as initial stack */ 202 #define CONFIG_L1_INIT_RAM 1 203 #define CFG_INIT_L1_LOCK 1 204 #define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */ 205 #define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */ 206 207 /* define to use L2SRAM as initial stack */ 208 #undef CONFIG_L2_INIT_RAM 209 #define CFG_INIT_L2_ADDR 0xf8fc0000 210 #define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */ 211 212 #ifdef CONFIG_L1_INIT_RAM 213 #define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR 214 #define CFG_INIT_RAM_END CFG_INIT_L1_END 215 #else 216 #define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR 217 #define CFG_INIT_RAM_END CFG_INIT_L2_END 218 #endif 219 220 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 221 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 222 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 223 224 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 225 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 226 227 /* Serial Port - controlled on board with jumper J8 228 * open - index 2 229 * shorted - index 1 230 */ 231 #define CONFIG_CONS_INDEX 1 232 #undef CONFIG_SERIAL_SOFTWARE_FIFO 233 #define CFG_NS16550 234 #define CFG_NS16550_SERIAL 235 #define CFG_NS16550_REG_SIZE 1 236 #define CFG_NS16550_CLK get_bus_freq(0) 237 238 #define CFG_BAUDRATE_TABLE \ 239 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 240 241 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 242 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 243 244 /* Use the HUSH parser */ 245 #define CFG_HUSH_PARSER 246 #ifdef CFG_HUSH_PARSER 247 #define CFG_PROMPT_HUSH_PS2 "> " 248 #endif 249 250 /* pass open firmware flat tree */ 251 #define CONFIG_OF_FLAT_TREE 1 252 #define CONFIG_OF_BOARD_SETUP 1 253 254 /* maximum size of the flat tree (8K) */ 255 #define OF_FLAT_TREE_MAX_SIZE 8192 256 257 #define OF_CPU "PowerPC,8544@0" 258 #define OF_SOC "soc8544@e0000000" 259 #define OF_TBCLK (bd->bi_busfreq / 8) 260 #define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500" 261 262 /* I2C */ 263 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 264 #define CONFIG_HARD_I2C /* I2C with hardware support */ 265 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 266 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 267 #define CFG_I2C_EEPROM_ADDR 0x57 268 #define CFG_I2C_SLAVE 0x7F 269 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 270 #define CFG_I2C_OFFSET 0x3100 271 272 /* 273 * General PCI 274 * Memory space is mapped 1-1, but I/O space must start from 0. 275 */ 276 #define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 277 #define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 278 279 #define CFG_PCI1_MEM_BASE 0xc0000000 280 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 281 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 282 #define CFG_PCI1_IO_BASE 0x00000000 283 #define CFG_PCI1_IO_PHYS 0xe1000000 284 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 285 286 /* PCI view of System Memory */ 287 #define CFG_PCI_MEMORY_BUS 0x00000000 288 #define CFG_PCI_MEMORY_PHYS 0x00000000 289 #define CFG_PCI_MEMORY_SIZE 0x80000000 290 291 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 292 #define CFG_PCIE2_MEM_BASE 0x80000000 293 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE 294 #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 295 #define CFG_PCIE2_IO_BASE 0x00000000 296 #define CFG_PCIE2_IO_PHYS 0xe2000000 297 #define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ 298 299 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 300 #define CFG_PCIE1_MEM_BASE 0xa0000000 301 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 302 #define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 303 #define CFG_PCIE1_MEM_BASE2 0xa8000000 304 #define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2 305 #define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */ 306 #define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */ 307 #define CFG_PCIE1_IO_PHYS 0xaf000000 308 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ 309 310 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 311 #define CFG_PCIE3_MEM_BASE 0xb0000000 312 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE 313 #define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 314 #define CFG_PCIE3_IO_BASE 0x00000000 315 #define CFG_PCIE3_IO_PHYS 0xe3000000 316 #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ 317 318 #if defined(CONFIG_PCI) 319 320 #define CONFIG_NET_MULTI 321 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 322 323 #undef CONFIG_EEPRO100 324 #undef CONFIG_TULIP 325 #define CONFIG_RTL8139 326 327 #ifdef CONFIG_RTL8139 328 /* This macro is used by RTL8139 but not defined in PPC architecture */ 329 #define KSEG1ADDR(x) (x) 330 #define _IO_BASE 0x00000000 331 #endif 332 333 #ifndef CONFIG_PCI_PNP 334 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE 335 #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE 336 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 337 #endif 338 339 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 340 #define CONFIG_DOS_PARTITION 341 #define CONFIG_SCSI_AHCI 342 343 #ifdef CONFIG_SCSI_AHCI 344 #define CONFIG_SATA_ULI5288 345 #define CFG_SCSI_MAX_SCSI_ID 4 346 #define CFG_SCSI_MAX_LUN 1 347 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 348 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 349 #endif /* SCSCI */ 350 351 #endif /* CONFIG_PCI */ 352 353 354 #if defined(CONFIG_TSEC_ENET) 355 356 #ifndef CONFIG_NET_MULTI 357 #define CONFIG_NET_MULTI 1 358 #endif 359 360 #define CONFIG_MII 1 /* MII PHY management */ 361 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 362 #define CONFIG_TSEC1 1 363 #define CONFIG_TSEC1_NAME "eTSEC1" 364 #define CONFIG_TSEC3 1 365 #define CONFIG_TSEC3_NAME "eTSEC3" 366 #undef CONFIG_MPC85XX_FEC 367 368 #define TSEC1_PHY_ADDR 0 369 #define TSEC3_PHY_ADDR 1 370 371 #define TSEC1_PHYIDX 0 372 #define TSEC3_PHYIDX 0 373 374 #define CONFIG_ETHPRIME "eTSEC1" 375 376 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 377 378 #endif /* CONFIG_TSEC_ENET */ 379 380 /* 381 * Environment 382 */ 383 #define CFG_ENV_IS_IN_FLASH 1 384 #if CFG_MONITOR_BASE > 0xfff80000 385 #define CFG_ENV_ADDR 0xfff80000 386 #else 387 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 388 #endif 389 #define CFG_ENV_SIZE 0x2000 390 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 391 392 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 393 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 394 395 #if defined(CONFIG_PCI) 396 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 397 | CFG_CMD_PCI \ 398 | CFG_CMD_PING \ 399 | CFG_CMD_I2C \ 400 | CFG_CMD_MII \ 401 | CFG_CMD_BEDBUG \ 402 | CFG_CMD_NET) 403 #else 404 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 405 | CFG_CMD_PING \ 406 | CFG_CMD_I2C \ 407 | CFG_CMD_MII) 408 #endif 409 #include <cmd_confdefs.h> 410 411 #undef CONFIG_WATCHDOG /* watchdog disabled */ 412 413 /* 414 * Miscellaneous configurable options 415 */ 416 #define CFG_LONGHELP /* undef to save memory */ 417 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 418 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 419 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 420 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 421 #else 422 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 423 #endif 424 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 425 #define CFG_MAXARGS 16 /* max number of command args */ 426 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 427 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 428 429 /* 430 * For booting Linux, the board info and command line data 431 * have to be in the first 8 MB of memory, since this is 432 * the maximum mapped by the Linux kernel during initialization. 433 */ 434 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 435 436 /* Cache Configuration */ 437 #define CFG_DCACHE_SIZE 32768 438 #define CFG_CACHELINE_SIZE 32 439 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 440 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 441 #endif 442 443 /* 444 * Internal Definitions 445 * 446 * Boot Flags 447 */ 448 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 449 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 450 451 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 452 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 453 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 454 #endif 455 456 /* 457 * Environment Configuration 458 */ 459 460 /* The mac addresses for all ethernet interface */ 461 #if defined(CONFIG_TSEC_ENET) 462 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 463 #define CONFIG_HAS_ETH1 464 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 465 #define CONFIG_HAS_ETH2 466 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 467 #define CONFIG_HAS_ETH3 468 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 469 #endif 470 471 #define CONFIG_IPADDR 192.168.1.251 472 473 #define CONFIG_HOSTNAME 8544ds_unknown 474 #define CONFIG_ROOTPATH /nfs/mpc85xx 475 #define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot 476 477 #define CONFIG_SERVERIP 192.168.0.1 478 #define CONFIG_GATEWAYIP 192.168.0.1 479 #define CONFIG_NETMASK 255.255.0.0 480 481 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 482 483 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 484 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 485 486 #define CONFIG_BAUDRATE 115200 487 488 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) 489 #define PCIE_ENV \ 490 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 491 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 492 "pcie1regs=setenv a e000a; run pciereg\0" \ 493 "pcie2regs=setenv a e0009; run pciereg\0" \ 494 "pcie3regs=setenv a e000b; run pciereg\0" \ 495 "pcieerr=md ${a}020 1; md ${a}e00;" \ 496 "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 497 "pci d.w $b.0 56 1;" \ 498 "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \ 499 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \ 500 "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \ 501 "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \ 502 "pci w $b.0 130 ffffffff\0" \ 503 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 504 "pcie1err=setenv a e000a; run pcieerr\0" \ 505 "pcie2err=setenv a e0009; run pcieerr\0" \ 506 "pcie3err=setenv a e000b; run pcieerr\0" \ 507 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 508 "pcie2errc=setenv a e0009; run pcieerrc\0" \ 509 "pcie3errc=setenv a e000b; run pcieerrc\0" 510 #else 511 #define PCIE_ENV "" 512 #endif 513 514 #if defined(CONFIG_PCI1) 515 #define PCI_ENV \ 516 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 517 "echo e;md ${a}e00 9\0" \ 518 "pci1regs=setenv a e0008; run pcireg\0" \ 519 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 520 "pci d.w $b.0 56 1\0" \ 521 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 522 "pci w.w $b.0 56 ffff\0" \ 523 "pci1err=setenv a e0008; run pcierr\0" \ 524 "pci1errc=setenv a e0008; run pcierrc\0" 525 #else 526 #define PCI_ENV "" 527 #endif 528 529 #if defined(CONFIG_TSEC_ENET) 530 #define ENET_ENV \ 531 "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ 532 "md ${a}098 2\0" \ 533 "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ 534 "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ 535 "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ 536 "echo mib;md ${a}680 31\0" \ 537 "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ 538 "enet1regs=setenv a e0024; run enetreg\0" \ 539 "enet3regs=setenv a e0026; run enetreg\0" 540 #else 541 #define ENET_ENV "" 542 #endif 543 544 #define CONFIG_EXTRA_ENV_SETTINGS \ 545 "netdev=eth0\0" \ 546 "consoledev=ttyS0\0" \ 547 "ramdiskaddr=2000000\0" \ 548 "ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \ 549 "fdtaddr=400000\0" \ 550 "fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \ 551 "eoi=mw e00400b0 0\0" \ 552 "iack=md e00400a0 1\0" \ 553 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ 554 "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ 555 "ddrregs=setenv a e0002; run ddrreg\0" \ 556 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ 557 "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ 558 "guregs=setenv a e00e0; run gureg\0" \ 559 "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ 560 "ecmregs=setenv a e0001; run ecmreg\0" \ 561 PCIE_ENV \ 562 PCI_ENV \ 563 ENET_ENV 564 565 566 #define CONFIG_NFSBOOTCOMMAND \ 567 "setenv bootargs root=/dev/nfs rw " \ 568 "nfsroot=$serverip:$rootpath " \ 569 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 570 "console=$consoledev,$baudrate $othbootargs;" \ 571 "tftp $loadaddr $bootfile;" \ 572 "tftp $fdtaddr $fdtfile;" \ 573 "bootm $loadaddr - $fdtaddr" 574 575 576 #define CONFIG_RAMBOOTCOMMAND \ 577 "setenv bootargs root=/dev/ram rw " \ 578 "console=$consoledev,$baudrate $othbootargs;" \ 579 "tftp $ramdiskaddr $ramdiskfile;" \ 580 "tftp $loadaddr $bootfile;" \ 581 "tftp $fdtaddr $fdtfile;" \ 582 "bootm $loadaddr $ramdiskaddr $fdtaddr" 583 584 #define CONFIG_BOOTCOMMAND \ 585 "setenv bootargs root=/dev/sda3 rw " \ 586 "console=$consoledev,$baudrate $othbootargs;" \ 587 "tftp $loadaddr $bootfile;" \ 588 "tftp $fdtaddr $fdtfile;" \ 589 "bootm $loadaddr - $fdtaddr" 590 591 #endif /* __CONFIG_H */ 592