1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8544ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifndef CONFIG_SYS_TEXT_BASE 15 #define CONFIG_SYS_TEXT_BASE 0xfff80000 16 #endif 17 18 #define CONFIG_PCI1 1 /* PCI controller 1 */ 19 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 20 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 21 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 22 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 23 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 24 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 25 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 26 27 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 28 #define CONFIG_ENV_OVERWRITE 29 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 30 31 #ifndef __ASSEMBLY__ 32 extern unsigned long get_board_sys_clk(unsigned long dummy); 33 #endif 34 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 35 36 /* 37 * These can be toggled for performance analysis, otherwise use default. 38 */ 39 #define CONFIG_L2_CACHE /* toggle L2 cache */ 40 #define CONFIG_BTB /* toggle branch predition */ 41 42 /* 43 * Only possible on E500 Version 2 or newer cores. 44 */ 45 #define CONFIG_ENABLE_36BIT_PHYS 1 46 47 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 48 #define CONFIG_SYS_MEMTEST_END 0x00400000 49 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 50 51 #define CONFIG_SYS_CCSRBAR 0xe0000000 52 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 53 54 /* DDR Setup */ 55 #undef CONFIG_FSL_DDR_INTERACTIVE 56 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 57 #define CONFIG_DDR_SPD 58 59 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 60 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 61 62 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 63 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 64 #define CONFIG_VERY_BIG_RAM 65 66 #define CONFIG_NUM_DDR_CONTROLLERS 1 67 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 68 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 69 70 /* I2C addresses of SPD EEPROMs */ 71 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 72 73 /* Make sure required options are set */ 74 #ifndef CONFIG_SPD_EEPROM 75 #error ("CONFIG_SPD_EEPROM is required") 76 #endif 77 78 #undef CONFIG_CLOCKS_IN_MHZ 79 80 /* 81 * Memory map 82 * 83 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 84 * 85 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 86 * 87 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 88 * 89 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 90 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 91 * 92 * Localbus cacheable 93 * 94 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 95 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 96 * 97 * Localbus non-cacheable 98 * 99 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 100 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 101 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 102 * 103 */ 104 105 /* 106 * Local Bus Definitions 107 */ 108 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 109 110 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 111 112 #define CONFIG_SYS_BR0_PRELIM 0xff801001 113 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 114 115 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 116 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 117 118 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 119 120 #define CONFIG_SYS_FLASH_QUIET_TEST 121 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 122 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 123 #undef CONFIG_SYS_FLASH_CHECKSUM 124 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 125 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 126 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 127 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 129 130 #define CONFIG_FLASH_CFI_DRIVER 131 #define CONFIG_SYS_FLASH_CFI 132 #define CONFIG_SYS_FLASH_EMPTY_INFO 133 134 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 135 136 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 137 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 138 139 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 140 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 141 142 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 143 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 144 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 145 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 146 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 147 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 148 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 149 * register */ 150 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 151 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 152 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 153 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 154 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 155 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 156 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 157 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 158 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 159 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 160 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 161 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 162 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 163 #define PIXIS_VSPEED2_TSEC1SER 0x2 164 #define PIXIS_VSPEED2_TSEC3SER 0x1 165 #define PIXIS_VCFGEN1_TSEC1SER 0x20 166 #define PIXIS_VCFGEN1_TSEC3SER 0x40 167 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 168 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 169 170 #define CONFIG_SYS_INIT_RAM_LOCK 1 171 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 172 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 173 174 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 175 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 176 177 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 178 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 179 180 /* Serial Port - controlled on board with jumper J8 181 * open - index 2 182 * shorted - index 1 183 */ 184 #define CONFIG_CONS_INDEX 1 185 #define CONFIG_SYS_NS16550_SERIAL 186 #define CONFIG_SYS_NS16550_REG_SIZE 1 187 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 188 189 #define CONFIG_SYS_BAUDRATE_TABLE \ 190 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 191 192 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 193 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 194 195 /* I2C */ 196 #define CONFIG_SYS_I2C 197 #define CONFIG_SYS_I2C_FSL 198 #define CONFIG_SYS_FSL_I2C_SPEED 400000 199 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 200 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 201 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 202 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 203 204 /* 205 * General PCI 206 * Memory space is mapped 1-1, but I/O space must start from 0. 207 */ 208 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 209 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 210 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 211 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 212 213 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 214 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 215 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 216 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 217 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 218 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 219 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 220 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 221 222 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 223 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 224 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 225 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 226 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 227 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 228 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 229 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 230 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 231 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 232 233 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 234 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 235 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 236 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 237 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 238 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 239 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 240 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 241 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 242 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 243 244 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 245 #define CONFIG_SYS_PCIE3_NAME "ULI" 246 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 247 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 248 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 249 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 250 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 251 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 252 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 253 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 254 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 255 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 256 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 257 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 258 259 #if defined(CONFIG_PCI) 260 261 /*PCIE video card used*/ 262 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 263 264 /*PCI video card used*/ 265 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 266 267 /* video */ 268 269 #if defined(CONFIG_VIDEO) 270 #define CONFIG_BIOSEMU 271 #define CONFIG_ATI_RADEON_FB 272 #define CONFIG_VIDEO_LOGO 273 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 274 #endif 275 276 #undef CONFIG_EEPRO100 277 #undef CONFIG_TULIP 278 279 #ifndef CONFIG_PCI_PNP 280 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 281 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 282 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 283 #endif 284 285 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 286 #define CONFIG_DOS_PARTITION 287 #define CONFIG_SCSI_AHCI 288 289 #ifdef CONFIG_SCSI_AHCI 290 #define CONFIG_LIBATA 291 #define CONFIG_SATA_ULI5288 292 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 293 #define CONFIG_SYS_SCSI_MAX_LUN 1 294 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 295 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 296 #endif /* SCSCI */ 297 298 #endif /* CONFIG_PCI */ 299 300 #if defined(CONFIG_TSEC_ENET) 301 302 #define CONFIG_MII 1 /* MII PHY management */ 303 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 304 #define CONFIG_TSEC1 1 305 #define CONFIG_TSEC1_NAME "eTSEC1" 306 #define CONFIG_TSEC3 1 307 #define CONFIG_TSEC3_NAME "eTSEC3" 308 309 #define CONFIG_PIXIS_SGMII_CMD 310 #define CONFIG_FSL_SGMII_RISER 1 311 #define SGMII_RISER_PHY_OFFSET 0x1c 312 313 #define TSEC1_PHY_ADDR 0 314 #define TSEC3_PHY_ADDR 1 315 316 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 317 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 318 319 #define TSEC1_PHYIDX 0 320 #define TSEC3_PHYIDX 0 321 322 #define CONFIG_ETHPRIME "eTSEC1" 323 324 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 325 #endif /* CONFIG_TSEC_ENET */ 326 327 /* 328 * Environment 329 */ 330 #define CONFIG_ENV_IS_IN_FLASH 1 331 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 332 #define CONFIG_ENV_ADDR 0xfff80000 333 #else 334 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) 335 #endif 336 #define CONFIG_ENV_SIZE 0x2000 337 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 338 339 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 340 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 341 342 /* 343 * BOOTP options 344 */ 345 #define CONFIG_BOOTP_BOOTFILESIZE 346 #define CONFIG_BOOTP_BOOTPATH 347 #define CONFIG_BOOTP_GATEWAY 348 #define CONFIG_BOOTP_HOSTNAME 349 350 /* 351 * Command line configuration. 352 */ 353 #define CONFIG_CMD_IRQ 354 #define CONFIG_CMD_REGINFO 355 356 #if defined(CONFIG_PCI) 357 #define CONFIG_CMD_PCI 358 #define CONFIG_SCSI 359 #endif 360 361 /* 362 * USB 363 */ 364 #define CONFIG_USB_EHCI 365 366 #ifdef CONFIG_USB_EHCI 367 #define CONFIG_USB_EHCI_PCI 368 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 369 #define CONFIG_PCI_EHCI_DEVICE 0 370 #endif 371 372 #undef CONFIG_WATCHDOG /* watchdog disabled */ 373 374 /* 375 * Miscellaneous configurable options 376 */ 377 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 378 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 379 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 380 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 381 #if defined(CONFIG_CMD_KGDB) 382 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 383 #else 384 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 385 #endif 386 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 387 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 388 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 389 390 /* 391 * For booting Linux, the board info and command line data 392 * have to be in the first 64 MB of memory, since this is 393 * the maximum mapped by the Linux kernel during initialization. 394 */ 395 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 396 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 397 398 #if defined(CONFIG_CMD_KGDB) 399 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 400 #endif 401 402 /* 403 * Environment Configuration 404 */ 405 406 /* The mac addresses for all ethernet interface */ 407 #if defined(CONFIG_TSEC_ENET) 408 #define CONFIG_HAS_ETH0 409 #define CONFIG_HAS_ETH1 410 #endif 411 412 #define CONFIG_IPADDR 192.168.1.251 413 414 #define CONFIG_HOSTNAME 8544ds_unknown 415 #define CONFIG_ROOTPATH "/nfs/mpc85xx" 416 #define CONFIG_BOOTFILE "8544ds/uImage.uboot" 417 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 418 419 #define CONFIG_SERVERIP 192.168.1.1 420 #define CONFIG_GATEWAYIP 192.168.1.1 421 #define CONFIG_NETMASK 255.255.0.0 422 423 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 424 425 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 426 427 #define CONFIG_BAUDRATE 115200 428 429 #define CONFIG_EXTRA_ENV_SETTINGS \ 430 "netdev=eth0\0" \ 431 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 432 "tftpflash=tftpboot $loadaddr $uboot; " \ 433 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 434 " +$filesize; " \ 435 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 436 " +$filesize; " \ 437 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 438 " $filesize; " \ 439 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 440 " +$filesize; " \ 441 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 442 " $filesize\0" \ 443 "consoledev=ttyS0\0" \ 444 "ramdiskaddr=2000000\0" \ 445 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 446 "fdtaddr=1e00000\0" \ 447 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 448 "bdev=sda3\0" 449 450 #define CONFIG_NFSBOOTCOMMAND \ 451 "setenv bootargs root=/dev/nfs rw " \ 452 "nfsroot=$serverip:$rootpath " \ 453 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 454 "console=$consoledev,$baudrate $othbootargs;" \ 455 "tftp $loadaddr $bootfile;" \ 456 "tftp $fdtaddr $fdtfile;" \ 457 "bootm $loadaddr - $fdtaddr" 458 459 #define CONFIG_RAMBOOTCOMMAND \ 460 "setenv bootargs root=/dev/ram rw " \ 461 "console=$consoledev,$baudrate $othbootargs;" \ 462 "tftp $ramdiskaddr $ramdiskfile;" \ 463 "tftp $loadaddr $bootfile;" \ 464 "tftp $fdtaddr $fdtfile;" \ 465 "bootm $loadaddr $ramdiskaddr $fdtaddr" 466 467 #define CONFIG_BOOTCOMMAND \ 468 "setenv bootargs root=/dev/$bdev rw " \ 469 "console=$consoledev,$baudrate $othbootargs;" \ 470 "tftp $loadaddr $bootfile;" \ 471 "tftp $fdtaddr $fdtfile;" \ 472 "bootm $loadaddr - $fdtaddr" 473 474 #endif /* __CONFIG_H */ 475