1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * mpc8544ds board configuration file 8 * 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_PCI1 1 /* PCI controller 1 */ 14 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 15 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 16 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 17 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 18 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 19 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 20 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 21 22 #define CONFIG_ENV_OVERWRITE 23 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 24 25 #ifndef __ASSEMBLY__ 26 extern unsigned long get_board_sys_clk(unsigned long dummy); 27 #endif 28 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 29 30 /* 31 * These can be toggled for performance analysis, otherwise use default. 32 */ 33 #define CONFIG_L2_CACHE /* toggle L2 cache */ 34 #define CONFIG_BTB /* toggle branch predition */ 35 36 /* 37 * Only possible on E500 Version 2 or newer cores. 38 */ 39 #define CONFIG_ENABLE_36BIT_PHYS 1 40 41 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 42 #define CONFIG_SYS_MEMTEST_END 0x00400000 43 44 #define CONFIG_SYS_CCSRBAR 0xe0000000 45 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 46 47 /* DDR Setup */ 48 #undef CONFIG_FSL_DDR_INTERACTIVE 49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 50 #define CONFIG_DDR_SPD 51 52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 53 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 54 55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 57 #define CONFIG_VERY_BIG_RAM 58 59 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 60 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 61 62 /* I2C addresses of SPD EEPROMs */ 63 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 64 65 /* Make sure required options are set */ 66 #ifndef CONFIG_SPD_EEPROM 67 #error ("CONFIG_SPD_EEPROM is required") 68 #endif 69 70 #undef CONFIG_CLOCKS_IN_MHZ 71 72 /* 73 * Memory map 74 * 75 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 76 * 77 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 78 * 79 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 80 * 81 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 82 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 83 * 84 * Localbus cacheable 85 * 86 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 87 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 88 * 89 * Localbus non-cacheable 90 * 91 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 92 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 93 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 94 * 95 */ 96 97 /* 98 * Local Bus Definitions 99 */ 100 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 101 102 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 103 104 #define CONFIG_SYS_BR0_PRELIM 0xff801001 105 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 106 107 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 108 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 109 110 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 111 112 #define CONFIG_SYS_FLASH_QUIET_TEST 113 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 114 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 115 #undef CONFIG_SYS_FLASH_CHECKSUM 116 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 117 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 118 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 119 120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 121 122 #define CONFIG_FLASH_CFI_DRIVER 123 #define CONFIG_SYS_FLASH_CFI 124 #define CONFIG_SYS_FLASH_EMPTY_INFO 125 126 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 127 128 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 129 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 130 131 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 132 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 133 134 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 135 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 136 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 137 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 138 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 139 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 140 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 141 * register */ 142 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 143 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 144 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 145 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 146 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 147 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 148 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 149 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 150 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 151 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 152 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 153 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 154 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 155 #define PIXIS_VSPEED2_TSEC1SER 0x2 156 #define PIXIS_VSPEED2_TSEC3SER 0x1 157 #define PIXIS_VCFGEN1_TSEC1SER 0x20 158 #define PIXIS_VCFGEN1_TSEC3SER 0x40 159 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 160 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 161 162 #define CONFIG_SYS_INIT_RAM_LOCK 1 163 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 164 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 165 166 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 167 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 168 169 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 170 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 171 172 /* Serial Port - controlled on board with jumper J8 173 * open - index 2 174 * shorted - index 1 175 */ 176 #define CONFIG_SYS_NS16550_SERIAL 177 #define CONFIG_SYS_NS16550_REG_SIZE 1 178 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 179 180 #define CONFIG_SYS_BAUDRATE_TABLE \ 181 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 182 183 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 184 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 185 186 /* I2C */ 187 #define CONFIG_SYS_I2C 188 #define CONFIG_SYS_I2C_FSL 189 #define CONFIG_SYS_FSL_I2C_SPEED 400000 190 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 191 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 192 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 193 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 194 195 /* 196 * General PCI 197 * Memory space is mapped 1-1, but I/O space must start from 0. 198 */ 199 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 200 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 201 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 202 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 203 204 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 205 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 206 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 207 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 208 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 209 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 210 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 211 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 212 213 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 214 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 215 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 216 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 217 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 218 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 219 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 220 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 221 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 222 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 223 224 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 225 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 226 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 227 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 228 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 229 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 230 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 231 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 232 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 233 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 234 235 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 236 #define CONFIG_SYS_PCIE3_NAME "ULI" 237 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 238 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 239 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 240 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 241 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 242 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 243 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 244 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 245 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 246 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 247 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 248 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 249 250 #if defined(CONFIG_PCI) 251 252 /*PCIE video card used*/ 253 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 254 255 /*PCI video card used*/ 256 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 257 258 /* video */ 259 260 #if defined(CONFIG_VIDEO) 261 #define CONFIG_BIOSEMU 262 #define CONFIG_ATI_RADEON_FB 263 #define CONFIG_VIDEO_LOGO 264 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 265 #endif 266 267 #undef CONFIG_EEPRO100 268 #undef CONFIG_TULIP 269 270 #ifndef CONFIG_PCI_PNP 271 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 272 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 273 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 274 #endif 275 276 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 277 278 #ifdef CONFIG_SCSI_AHCI 279 #define CONFIG_SATA_ULI5288 280 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 281 #define CONFIG_SYS_SCSI_MAX_LUN 1 282 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 283 #endif /* CONFIG_SCSI_AHCI */ 284 285 #endif /* CONFIG_PCI */ 286 287 #if defined(CONFIG_TSEC_ENET) 288 289 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 290 #define CONFIG_TSEC1 1 291 #define CONFIG_TSEC1_NAME "eTSEC1" 292 #define CONFIG_TSEC3 1 293 #define CONFIG_TSEC3_NAME "eTSEC3" 294 295 #define CONFIG_PIXIS_SGMII_CMD 296 #define CONFIG_FSL_SGMII_RISER 1 297 #define SGMII_RISER_PHY_OFFSET 0x1c 298 299 #define TSEC1_PHY_ADDR 0 300 #define TSEC3_PHY_ADDR 1 301 302 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 303 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 304 305 #define TSEC1_PHYIDX 0 306 #define TSEC3_PHYIDX 0 307 308 #define CONFIG_ETHPRIME "eTSEC1" 309 #endif /* CONFIG_TSEC_ENET */ 310 311 /* 312 * Environment 313 */ 314 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 315 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 316 #define CONFIG_ENV_ADDR 0xfff80000 317 #else 318 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 319 #endif 320 #define CONFIG_ENV_SIZE 0x2000 321 322 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 323 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 324 325 /* 326 * BOOTP options 327 */ 328 #define CONFIG_BOOTP_BOOTFILESIZE 329 330 /* 331 * USB 332 */ 333 334 #ifdef CONFIG_USB_EHCI_HCD 335 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 336 #define CONFIG_PCI_EHCI_DEVICE 0 337 #endif 338 339 #undef CONFIG_WATCHDOG /* watchdog disabled */ 340 341 /* 342 * Miscellaneous configurable options 343 */ 344 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 345 346 /* 347 * For booting Linux, the board info and command line data 348 * have to be in the first 64 MB of memory, since this is 349 * the maximum mapped by the Linux kernel during initialization. 350 */ 351 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 352 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 353 354 #if defined(CONFIG_CMD_KGDB) 355 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 356 #endif 357 358 /* 359 * Environment Configuration 360 */ 361 362 /* The mac addresses for all ethernet interface */ 363 #if defined(CONFIG_TSEC_ENET) 364 #define CONFIG_HAS_ETH0 365 #define CONFIG_HAS_ETH1 366 #endif 367 368 #define CONFIG_IPADDR 192.168.1.251 369 370 #define CONFIG_HOSTNAME "8544ds_unknown" 371 #define CONFIG_ROOTPATH "/nfs/mpc85xx" 372 #define CONFIG_BOOTFILE "8544ds/uImage.uboot" 373 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 374 375 #define CONFIG_SERVERIP 192.168.1.1 376 #define CONFIG_GATEWAYIP 192.168.1.1 377 #define CONFIG_NETMASK 255.255.0.0 378 379 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 380 381 #define CONFIG_EXTRA_ENV_SETTINGS \ 382 "netdev=eth0\0" \ 383 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 384 "tftpflash=tftpboot $loadaddr $uboot; " \ 385 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 386 " +$filesize; " \ 387 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 388 " +$filesize; " \ 389 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 390 " $filesize; " \ 391 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 392 " +$filesize; " \ 393 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 394 " $filesize\0" \ 395 "consoledev=ttyS0\0" \ 396 "ramdiskaddr=2000000\0" \ 397 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 398 "fdtaddr=1e00000\0" \ 399 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 400 "bdev=sda3\0" 401 402 #define CONFIG_NFSBOOTCOMMAND \ 403 "setenv bootargs root=/dev/nfs rw " \ 404 "nfsroot=$serverip:$rootpath " \ 405 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 406 "console=$consoledev,$baudrate $othbootargs;" \ 407 "tftp $loadaddr $bootfile;" \ 408 "tftp $fdtaddr $fdtfile;" \ 409 "bootm $loadaddr - $fdtaddr" 410 411 #define CONFIG_RAMBOOTCOMMAND \ 412 "setenv bootargs root=/dev/ram rw " \ 413 "console=$consoledev,$baudrate $othbootargs;" \ 414 "tftp $ramdiskaddr $ramdiskfile;" \ 415 "tftp $loadaddr $bootfile;" \ 416 "tftp $fdtaddr $fdtfile;" \ 417 "bootm $loadaddr $ramdiskaddr $fdtaddr" 418 419 #define CONFIG_BOOTCOMMAND \ 420 "setenv bootargs root=/dev/$bdev rw " \ 421 "console=$consoledev,$baudrate $othbootargs;" \ 422 "tftp $loadaddr $bootfile;" \ 423 "tftp $fdtaddr $fdtfile;" \ 424 "bootm $loadaddr - $fdtaddr" 425 426 #endif /* __CONFIG_H */ 427