1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8544ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8544 1 35 #define CONFIG_MPC8544DS 1 36 37 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 38 #define CONFIG_PCI1 1 /* PCI controller 1 */ 39 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 40 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 41 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 44 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 48 #define CONFIG_ENV_OVERWRITE 49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 50 #undef CONFIG_DDR_DLL 51 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 52 53 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 55 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 56 57 #define CONFIG_DDR_ECC_CMD 58 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 59 60 /* 61 * When initializing flash, if we cannot find the manufacturer ID, 62 * assume this is the AMD flash associated with the CDS board. 63 * This allows booting from a promjet. 64 */ 65 #define CONFIG_ASSUME_AMD_FLASH 66 67 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 68 69 #ifndef __ASSEMBLY__ 70 extern unsigned long get_board_sys_clk(unsigned long dummy); 71 #endif 72 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 73 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_L2_CACHE /* toggle L2 cache */ 78 #define CONFIG_BTB /* toggle branch predition */ 79 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 80 #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ 81 82 /* 83 * Only possible on E500 Version 2 or newer cores. 84 */ 85 #define CONFIG_ENABLE_36BIT_PHYS 1 86 87 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 88 89 #undef CFG_DRAM_TEST /* memory test, takes time */ 90 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 91 #define CFG_MEMTEST_END 0x00400000 92 #define CFG_ALT_MEMTEST 93 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 94 95 /* 96 * Base addresses -- Note these are effective addresses where the 97 * actual resources get mapped (not physical addresses) 98 */ 99 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 100 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 101 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 102 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 103 104 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 105 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 106 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) 107 #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) 108 109 /* 110 * DDR Setup 111 */ 112 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 113 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 114 115 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 116 117 /* 118 * Make sure required options are set 119 */ 120 #ifndef CONFIG_SPD_EEPROM 121 #error ("CONFIG_SPD_EEPROM is required") 122 #endif 123 124 #undef CONFIG_CLOCKS_IN_MHZ 125 126 /* 127 * Memory map 128 * 129 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 130 * 131 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 132 * 133 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 134 * 135 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 136 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 137 * 138 * Localbus cacheable 139 * 140 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 141 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 142 * 143 * Localbus non-cacheable 144 * 145 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 146 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 147 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 148 * 149 */ 150 151 /* 152 * Local Bus Definitions 153 */ 154 #define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */ 155 156 #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 157 158 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 159 160 #define CFG_BR0_PRELIM 0xff801001 161 #define CFG_BR1_PRELIM 0xfe801001 162 163 #define CFG_OR0_PRELIM 0xff806e65 164 #define CFG_OR1_PRELIM 0xff806e65 165 166 #define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE} 167 168 #define CFG_FLASH_QUIET_TEST 169 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 170 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 171 #undef CFG_FLASH_CHECKSUM 172 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 173 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 174 175 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 176 177 #define CFG_FLASH_CFI_DRIVER 178 #define CFG_FLASH_CFI 179 #define CFG_FLASH_EMPTY_INFO 180 181 #define CFG_LBC_NONCACHE_BASE 0xf8000000 182 183 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ 184 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 185 186 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ 187 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 188 189 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 190 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 191 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 192 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 193 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 194 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 195 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 196 * register */ 197 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 198 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 199 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 200 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 201 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 202 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 203 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 204 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 205 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 206 #define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 207 208 209 /* define to use L1 as initial stack */ 210 #define CONFIG_L1_INIT_RAM 1 211 #define CFG_INIT_L1_LOCK 1 212 #define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */ 213 #define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */ 214 215 /* define to use L2SRAM as initial stack */ 216 #undef CONFIG_L2_INIT_RAM 217 #define CFG_INIT_L2_ADDR 0xf8fc0000 218 #define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */ 219 220 #ifdef CONFIG_L1_INIT_RAM 221 #define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR 222 #define CFG_INIT_RAM_END CFG_INIT_L1_END 223 #else 224 #define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR 225 #define CFG_INIT_RAM_END CFG_INIT_L2_END 226 #endif 227 228 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 229 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 230 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 231 232 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 233 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 234 235 /* Serial Port - controlled on board with jumper J8 236 * open - index 2 237 * shorted - index 1 238 */ 239 #define CONFIG_CONS_INDEX 1 240 #undef CONFIG_SERIAL_SOFTWARE_FIFO 241 #define CFG_NS16550 242 #define CFG_NS16550_SERIAL 243 #define CFG_NS16550_REG_SIZE 1 244 #define CFG_NS16550_CLK get_bus_freq(0) 245 246 #define CFG_BAUDRATE_TABLE \ 247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 248 249 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 250 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 251 252 /* Use the HUSH parser */ 253 #define CFG_HUSH_PARSER 254 #ifdef CFG_HUSH_PARSER 255 #define CFG_PROMPT_HUSH_PS2 "> " 256 #endif 257 258 /* pass open firmware flat tree */ 259 #define CONFIG_OF_LIBFDT 1 260 #define CONFIG_OF_BOARD_SETUP 1 261 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 262 263 /* I2C */ 264 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 265 #define CONFIG_HARD_I2C /* I2C with hardware support */ 266 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 267 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 268 #define CFG_I2C_EEPROM_ADDR 0x57 269 #define CFG_I2C_SLAVE 0x7F 270 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 271 #define CFG_I2C_OFFSET 0x3100 272 273 /* 274 * General PCI 275 * Memory space is mapped 1-1, but I/O space must start from 0. 276 */ 277 #define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 278 #define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 279 280 #define CFG_PCI1_MEM_BASE 0xc0000000 281 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 282 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 283 #define CFG_PCI1_IO_BASE 0x00000000 284 #define CFG_PCI1_IO_PHYS 0xe1000000 285 #define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */ 286 287 /* PCI view of System Memory */ 288 #define CFG_PCI_MEMORY_BUS 0x00000000 289 #define CFG_PCI_MEMORY_PHYS 0x00000000 290 #define CFG_PCI_MEMORY_SIZE 0x80000000 291 292 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 293 #define CFG_PCIE2_MEM_BASE 0x80000000 294 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE 295 #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 296 #define CFG_PCIE2_IO_BASE 0x00000000 297 #define CFG_PCIE2_IO_PHYS 0xe1010000 298 #define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */ 299 300 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 301 #define CFG_PCIE1_MEM_BASE 0xa0000000 302 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 303 #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 304 #define CFG_PCIE1_IO_BASE 0x00000000 305 #define CFG_PCIE1_IO_PHYS 0xe1020000 306 #define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */ 307 308 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 309 #define CFG_PCIE3_MEM_BASE 0xb0000000 310 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE 311 #define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 312 #define CFG_PCIE3_IO_BASE 0x00000000 313 #define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 314 #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ 315 #define CFG_PCIE3_MEM_BASE2 0xb0200000 316 #define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2 317 #define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 318 319 #if defined(CONFIG_PCI) 320 321 #define CONFIG_NET_MULTI 322 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 323 324 #undef CONFIG_EEPRO100 325 #undef CONFIG_TULIP 326 #define CONFIG_RTL8139 327 328 #ifdef CONFIG_RTL8139 329 /* This macro is used by RTL8139 but not defined in PPC architecture */ 330 #define KSEG1ADDR(x) (x) 331 #define _IO_BASE 0x00000000 332 #endif 333 334 #ifndef CONFIG_PCI_PNP 335 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE 336 #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE 337 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 338 #endif 339 340 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 341 #define CONFIG_DOS_PARTITION 342 #define CONFIG_SCSI_AHCI 343 344 #ifdef CONFIG_SCSI_AHCI 345 #define CONFIG_SATA_ULI5288 346 #define CFG_SCSI_MAX_SCSI_ID 4 347 #define CFG_SCSI_MAX_LUN 1 348 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 349 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 350 #endif /* SCSCI */ 351 352 #endif /* CONFIG_PCI */ 353 354 355 #if defined(CONFIG_TSEC_ENET) 356 357 #ifndef CONFIG_NET_MULTI 358 #define CONFIG_NET_MULTI 1 359 #endif 360 361 #define CONFIG_MII 1 /* MII PHY management */ 362 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 363 #define CONFIG_TSEC1 1 364 #define CONFIG_TSEC1_NAME "eTSEC1" 365 #define CONFIG_TSEC3 1 366 #define CONFIG_TSEC3_NAME "eTSEC3" 367 368 #define TSEC1_PHY_ADDR 0 369 #define TSEC3_PHY_ADDR 1 370 371 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 372 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 373 374 #define TSEC1_PHYIDX 0 375 #define TSEC3_PHYIDX 0 376 377 #define CONFIG_ETHPRIME "eTSEC1" 378 379 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 380 #endif /* CONFIG_TSEC_ENET */ 381 382 /* 383 * Environment 384 */ 385 #define CFG_ENV_IS_IN_FLASH 1 386 #if CFG_MONITOR_BASE > 0xfff80000 387 #define CFG_ENV_ADDR 0xfff80000 388 #else 389 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 390 #endif 391 #define CFG_ENV_SIZE 0x2000 392 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 393 394 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 395 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 396 397 /* 398 * BOOTP options 399 */ 400 #define CONFIG_BOOTP_BOOTFILESIZE 401 #define CONFIG_BOOTP_BOOTPATH 402 #define CONFIG_BOOTP_GATEWAY 403 #define CONFIG_BOOTP_HOSTNAME 404 405 406 /* 407 * Command line configuration. 408 */ 409 #include <config_cmd_default.h> 410 411 #define CONFIG_CMD_PING 412 #define CONFIG_CMD_I2C 413 #define CONFIG_CMD_MII 414 #define CONFIG_CMD_ELF 415 416 #if defined(CONFIG_PCI) 417 #define CONFIG_CMD_PCI 418 #define CONFIG_CMD_BEDBUG 419 #define CONFIG_CMD_NET 420 #define CONFIG_CMD_SCSI 421 #define CONFIG_CMD_EXT2 422 #endif 423 424 425 #undef CONFIG_WATCHDOG /* watchdog disabled */ 426 427 /* 428 * Miscellaneous configurable options 429 */ 430 #define CFG_LONGHELP /* undef to save memory */ 431 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 432 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 433 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 434 #if defined(CONFIG_CMD_KGDB) 435 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 436 #else 437 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 438 #endif 439 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 440 #define CFG_MAXARGS 16 /* max number of command args */ 441 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 442 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 443 444 /* 445 * For booting Linux, the board info and command line data 446 * have to be in the first 8 MB of memory, since this is 447 * the maximum mapped by the Linux kernel during initialization. 448 */ 449 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 450 451 /* 452 * Internal Definitions 453 * 454 * Boot Flags 455 */ 456 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 457 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 458 459 #if defined(CONFIG_CMD_KGDB) 460 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 461 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 462 #endif 463 464 /* 465 * Environment Configuration 466 */ 467 468 /* The mac addresses for all ethernet interface */ 469 #if defined(CONFIG_TSEC_ENET) 470 #define CONFIG_HAS_ETH0 471 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 472 #define CONFIG_HAS_ETH1 473 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 474 #endif 475 476 #define CONFIG_IPADDR 192.168.1.251 477 478 #define CONFIG_HOSTNAME 8544ds_unknown 479 #define CONFIG_ROOTPATH /nfs/mpc85xx 480 #define CONFIG_BOOTFILE 8544ds/uImage.uboot 481 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 482 483 #define CONFIG_SERVERIP 192.168.1.1 484 #define CONFIG_GATEWAYIP 192.168.1.1 485 #define CONFIG_NETMASK 255.255.0.0 486 487 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 488 489 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 490 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 491 492 #define CONFIG_BAUDRATE 115200 493 494 #define CONFIG_EXTRA_ENV_SETTINGS \ 495 "netdev=eth0\0" \ 496 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 497 "tftpflash=tftpboot $loadaddr $uboot; " \ 498 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 499 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 500 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 501 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 502 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 503 "consoledev=ttyS0\0" \ 504 "ramdiskaddr=2000000\0" \ 505 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 506 "fdtaddr=c00000\0" \ 507 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 508 "bdev=sda3\0" 509 510 #define CONFIG_NFSBOOTCOMMAND \ 511 "setenv bootargs root=/dev/nfs rw " \ 512 "nfsroot=$serverip:$rootpath " \ 513 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 514 "console=$consoledev,$baudrate $othbootargs;" \ 515 "tftp $loadaddr $bootfile;" \ 516 "tftp $fdtaddr $fdtfile;" \ 517 "bootm $loadaddr - $fdtaddr" 518 519 #define CONFIG_RAMBOOTCOMMAND \ 520 "setenv bootargs root=/dev/ram rw " \ 521 "console=$consoledev,$baudrate $othbootargs;" \ 522 "tftp $ramdiskaddr $ramdiskfile;" \ 523 "tftp $loadaddr $bootfile;" \ 524 "tftp $fdtaddr $fdtfile;" \ 525 "bootm $loadaddr $ramdiskaddr $fdtaddr" 526 527 #define CONFIG_BOOTCOMMAND \ 528 "setenv bootargs root=/dev/$bdev rw " \ 529 "console=$consoledev,$baudrate $othbootargs;" \ 530 "tftp $loadaddr $bootfile;" \ 531 "tftp $fdtaddr $fdtfile;" \ 532 "bootm $loadaddr - $fdtaddr" 533 534 #endif /* __CONFIG_H */ 535