1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8544ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifndef CONFIG_SYS_TEXT_BASE 15 #define CONFIG_SYS_TEXT_BASE 0xfff80000 16 #endif 17 18 #define CONFIG_PCI1 1 /* PCI controller 1 */ 19 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 20 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 21 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 22 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 23 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 24 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 25 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 26 27 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 28 #define CONFIG_ENV_OVERWRITE 29 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 30 31 #ifndef __ASSEMBLY__ 32 extern unsigned long get_board_sys_clk(unsigned long dummy); 33 #endif 34 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 35 36 /* 37 * These can be toggled for performance analysis, otherwise use default. 38 */ 39 #define CONFIG_L2_CACHE /* toggle L2 cache */ 40 #define CONFIG_BTB /* toggle branch predition */ 41 42 /* 43 * Only possible on E500 Version 2 or newer cores. 44 */ 45 #define CONFIG_ENABLE_36BIT_PHYS 1 46 47 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 48 #define CONFIG_SYS_MEMTEST_END 0x00400000 49 50 #define CONFIG_SYS_CCSRBAR 0xe0000000 51 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 52 53 /* DDR Setup */ 54 #undef CONFIG_FSL_DDR_INTERACTIVE 55 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 56 #define CONFIG_DDR_SPD 57 58 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 59 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 60 61 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 62 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 63 #define CONFIG_VERY_BIG_RAM 64 65 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 66 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 67 68 /* I2C addresses of SPD EEPROMs */ 69 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 70 71 /* Make sure required options are set */ 72 #ifndef CONFIG_SPD_EEPROM 73 #error ("CONFIG_SPD_EEPROM is required") 74 #endif 75 76 #undef CONFIG_CLOCKS_IN_MHZ 77 78 /* 79 * Memory map 80 * 81 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 82 * 83 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 84 * 85 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 86 * 87 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 88 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 89 * 90 * Localbus cacheable 91 * 92 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 93 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 94 * 95 * Localbus non-cacheable 96 * 97 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 98 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 99 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 100 * 101 */ 102 103 /* 104 * Local Bus Definitions 105 */ 106 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 107 108 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 109 110 #define CONFIG_SYS_BR0_PRELIM 0xff801001 111 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 112 113 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 114 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 115 116 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 117 118 #define CONFIG_SYS_FLASH_QUIET_TEST 119 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 120 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 121 #undef CONFIG_SYS_FLASH_CHECKSUM 122 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 123 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 124 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 125 126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 127 128 #define CONFIG_FLASH_CFI_DRIVER 129 #define CONFIG_SYS_FLASH_CFI 130 #define CONFIG_SYS_FLASH_EMPTY_INFO 131 132 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 133 134 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 135 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 136 137 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 138 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 139 140 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 141 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 142 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 143 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 144 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 145 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 146 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 147 * register */ 148 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 149 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 150 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 151 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 152 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 153 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 154 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 155 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 156 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 157 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 158 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 159 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 160 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 161 #define PIXIS_VSPEED2_TSEC1SER 0x2 162 #define PIXIS_VSPEED2_TSEC3SER 0x1 163 #define PIXIS_VCFGEN1_TSEC1SER 0x20 164 #define PIXIS_VCFGEN1_TSEC3SER 0x40 165 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 166 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 167 168 #define CONFIG_SYS_INIT_RAM_LOCK 1 169 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 170 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 171 172 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 173 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 174 175 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 176 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 177 178 /* Serial Port - controlled on board with jumper J8 179 * open - index 2 180 * shorted - index 1 181 */ 182 #define CONFIG_CONS_INDEX 1 183 #define CONFIG_SYS_NS16550_SERIAL 184 #define CONFIG_SYS_NS16550_REG_SIZE 1 185 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 186 187 #define CONFIG_SYS_BAUDRATE_TABLE \ 188 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 189 190 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 191 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 192 193 /* I2C */ 194 #define CONFIG_SYS_I2C 195 #define CONFIG_SYS_I2C_FSL 196 #define CONFIG_SYS_FSL_I2C_SPEED 400000 197 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 198 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 199 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 200 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 201 202 /* 203 * General PCI 204 * Memory space is mapped 1-1, but I/O space must start from 0. 205 */ 206 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 207 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 208 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 209 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 210 211 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 212 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 213 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 214 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 215 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 216 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 217 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 218 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 219 220 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 221 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 222 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 223 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 224 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 225 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 226 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 227 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 228 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 229 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 230 231 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 232 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 233 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 234 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 235 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 236 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 237 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 238 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 239 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 240 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 241 242 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 243 #define CONFIG_SYS_PCIE3_NAME "ULI" 244 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 245 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 246 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 247 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 248 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 249 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 250 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 251 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 252 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 253 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 254 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 255 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 256 257 #if defined(CONFIG_PCI) 258 259 /*PCIE video card used*/ 260 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 261 262 /*PCI video card used*/ 263 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 264 265 /* video */ 266 267 #if defined(CONFIG_VIDEO) 268 #define CONFIG_BIOSEMU 269 #define CONFIG_ATI_RADEON_FB 270 #define CONFIG_VIDEO_LOGO 271 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 272 #endif 273 274 #undef CONFIG_EEPRO100 275 #undef CONFIG_TULIP 276 277 #ifndef CONFIG_PCI_PNP 278 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 279 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 280 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 281 #endif 282 283 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 284 285 #ifdef CONFIG_SCSI_AHCI 286 #define CONFIG_SATA_ULI5288 287 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 288 #define CONFIG_SYS_SCSI_MAX_LUN 1 289 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 290 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 291 #endif /* SCSCI */ 292 293 #endif /* CONFIG_PCI */ 294 295 #if defined(CONFIG_TSEC_ENET) 296 297 #define CONFIG_MII 1 /* MII PHY management */ 298 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 299 #define CONFIG_TSEC1 1 300 #define CONFIG_TSEC1_NAME "eTSEC1" 301 #define CONFIG_TSEC3 1 302 #define CONFIG_TSEC3_NAME "eTSEC3" 303 304 #define CONFIG_PIXIS_SGMII_CMD 305 #define CONFIG_FSL_SGMII_RISER 1 306 #define SGMII_RISER_PHY_OFFSET 0x1c 307 308 #define TSEC1_PHY_ADDR 0 309 #define TSEC3_PHY_ADDR 1 310 311 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 312 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 313 314 #define TSEC1_PHYIDX 0 315 #define TSEC3_PHYIDX 0 316 317 #define CONFIG_ETHPRIME "eTSEC1" 318 #endif /* CONFIG_TSEC_ENET */ 319 320 /* 321 * Environment 322 */ 323 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 324 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 325 #define CONFIG_ENV_ADDR 0xfff80000 326 #else 327 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 328 #endif 329 #define CONFIG_ENV_SIZE 0x2000 330 331 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 332 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 333 334 /* 335 * BOOTP options 336 */ 337 #define CONFIG_BOOTP_BOOTFILESIZE 338 #define CONFIG_BOOTP_BOOTPATH 339 #define CONFIG_BOOTP_GATEWAY 340 #define CONFIG_BOOTP_HOSTNAME 341 342 /* 343 * USB 344 */ 345 346 #ifdef CONFIG_USB_EHCI_HCD 347 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 348 #define CONFIG_PCI_EHCI_DEVICE 0 349 #endif 350 351 #undef CONFIG_WATCHDOG /* watchdog disabled */ 352 353 /* 354 * Miscellaneous configurable options 355 */ 356 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 357 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 358 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 359 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 360 361 /* 362 * For booting Linux, the board info and command line data 363 * have to be in the first 64 MB of memory, since this is 364 * the maximum mapped by the Linux kernel during initialization. 365 */ 366 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 367 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 368 369 #if defined(CONFIG_CMD_KGDB) 370 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 371 #endif 372 373 /* 374 * Environment Configuration 375 */ 376 377 /* The mac addresses for all ethernet interface */ 378 #if defined(CONFIG_TSEC_ENET) 379 #define CONFIG_HAS_ETH0 380 #define CONFIG_HAS_ETH1 381 #endif 382 383 #define CONFIG_IPADDR 192.168.1.251 384 385 #define CONFIG_HOSTNAME 8544ds_unknown 386 #define CONFIG_ROOTPATH "/nfs/mpc85xx" 387 #define CONFIG_BOOTFILE "8544ds/uImage.uboot" 388 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 389 390 #define CONFIG_SERVERIP 192.168.1.1 391 #define CONFIG_GATEWAYIP 192.168.1.1 392 #define CONFIG_NETMASK 255.255.0.0 393 394 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 395 396 #define CONFIG_EXTRA_ENV_SETTINGS \ 397 "netdev=eth0\0" \ 398 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 399 "tftpflash=tftpboot $loadaddr $uboot; " \ 400 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 401 " +$filesize; " \ 402 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 403 " +$filesize; " \ 404 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 405 " $filesize; " \ 406 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 407 " +$filesize; " \ 408 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 409 " $filesize\0" \ 410 "consoledev=ttyS0\0" \ 411 "ramdiskaddr=2000000\0" \ 412 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 413 "fdtaddr=1e00000\0" \ 414 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 415 "bdev=sda3\0" 416 417 #define CONFIG_NFSBOOTCOMMAND \ 418 "setenv bootargs root=/dev/nfs rw " \ 419 "nfsroot=$serverip:$rootpath " \ 420 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 421 "console=$consoledev,$baudrate $othbootargs;" \ 422 "tftp $loadaddr $bootfile;" \ 423 "tftp $fdtaddr $fdtfile;" \ 424 "bootm $loadaddr - $fdtaddr" 425 426 #define CONFIG_RAMBOOTCOMMAND \ 427 "setenv bootargs root=/dev/ram rw " \ 428 "console=$consoledev,$baudrate $othbootargs;" \ 429 "tftp $ramdiskaddr $ramdiskfile;" \ 430 "tftp $loadaddr $bootfile;" \ 431 "tftp $fdtaddr $fdtfile;" \ 432 "bootm $loadaddr $ramdiskaddr $fdtaddr" 433 434 #define CONFIG_BOOTCOMMAND \ 435 "setenv bootargs root=/dev/$bdev rw " \ 436 "console=$consoledev,$baudrate $othbootargs;" \ 437 "tftp $loadaddr $bootfile;" \ 438 "tftp $fdtaddr $fdtfile;" \ 439 "bootm $loadaddr - $fdtaddr" 440 441 #endif /* __CONFIG_H */ 442