1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8544ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8544 1 35 #define CONFIG_MPC8544DS 1 36 37 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 38 #define CONFIG_PCI1 1 /* PCI controller 1 */ 39 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 40 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 41 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 44 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 48 #define CONFIG_ENV_OVERWRITE 49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 50 #undef CONFIG_DDR_DLL 51 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 52 53 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 55 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 56 57 #define CONFIG_DDR_ECC_CMD 58 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 59 60 /* 61 * When initializing flash, if we cannot find the manufacturer ID, 62 * assume this is the AMD flash associated with the CDS board. 63 * This allows booting from a promjet. 64 */ 65 #define CONFIG_ASSUME_AMD_FLASH 66 67 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 68 69 #ifndef __ASSEMBLY__ 70 extern unsigned long get_board_sys_clk(unsigned long dummy); 71 #endif 72 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 73 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_L2_CACHE /* toggle L2 cache */ 78 #define CONFIG_BTB /* toggle branch predition */ 79 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 80 81 /* 82 * Only possible on E500 Version 2 or newer cores. 83 */ 84 #define CONFIG_ENABLE_36BIT_PHYS 1 85 86 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 87 #define CFG_MEMTEST_END 0x00400000 88 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 89 90 /* 91 * Base addresses -- Note these are effective addresses where the 92 * actual resources get mapped (not physical addresses) 93 */ 94 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 95 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 96 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 97 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 98 99 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 100 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 101 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) 102 #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) 103 104 /* 105 * DDR Setup 106 */ 107 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 108 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 109 110 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 111 112 /* 113 * Make sure required options are set 114 */ 115 #ifndef CONFIG_SPD_EEPROM 116 #error ("CONFIG_SPD_EEPROM is required") 117 #endif 118 119 #undef CONFIG_CLOCKS_IN_MHZ 120 121 /* 122 * Memory map 123 * 124 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 125 * 126 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 127 * 128 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 129 * 130 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 131 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 132 * 133 * Localbus cacheable 134 * 135 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 136 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 137 * 138 * Localbus non-cacheable 139 * 140 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 141 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 142 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 143 * 144 */ 145 146 /* 147 * Local Bus Definitions 148 */ 149 #define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */ 150 151 #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 152 153 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 154 155 #define CFG_BR0_PRELIM 0xff801001 156 #define CFG_BR1_PRELIM 0xfe801001 157 158 #define CFG_OR0_PRELIM 0xff806e65 159 #define CFG_OR1_PRELIM 0xff806e65 160 161 #define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE} 162 163 #define CFG_FLASH_QUIET_TEST 164 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 165 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 166 #undef CFG_FLASH_CHECKSUM 167 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 168 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 169 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 170 171 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 172 173 #define CFG_FLASH_CFI_DRIVER 174 #define CFG_FLASH_CFI 175 #define CFG_FLASH_EMPTY_INFO 176 177 #define CFG_LBC_NONCACHE_BASE 0xf8000000 178 179 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ 180 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 181 182 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ 183 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 184 185 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 186 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 187 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 188 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 189 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 190 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 191 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 192 * register */ 193 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 194 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 195 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 196 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 197 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 198 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 199 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 200 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 201 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 202 #define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 203 204 205 /* define to use L1 as initial stack */ 206 #define CONFIG_L1_INIT_RAM 1 207 #define CFG_INIT_L1_LOCK 1 208 #define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */ 209 #define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */ 210 211 /* define to use L2SRAM as initial stack */ 212 #undef CONFIG_L2_INIT_RAM 213 #define CFG_INIT_L2_ADDR 0xf8fc0000 214 #define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */ 215 216 #ifdef CONFIG_L1_INIT_RAM 217 #define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR 218 #define CFG_INIT_RAM_END CFG_INIT_L1_END 219 #else 220 #define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR 221 #define CFG_INIT_RAM_END CFG_INIT_L2_END 222 #endif 223 224 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 225 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 226 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 227 228 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 229 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 230 231 /* Serial Port - controlled on board with jumper J8 232 * open - index 2 233 * shorted - index 1 234 */ 235 #define CONFIG_CONS_INDEX 1 236 #undef CONFIG_SERIAL_SOFTWARE_FIFO 237 #define CFG_NS16550 238 #define CFG_NS16550_SERIAL 239 #define CFG_NS16550_REG_SIZE 1 240 #define CFG_NS16550_CLK get_bus_freq(0) 241 242 #define CFG_BAUDRATE_TABLE \ 243 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 244 245 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 246 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 247 248 /* Use the HUSH parser */ 249 #define CFG_HUSH_PARSER 250 #ifdef CFG_HUSH_PARSER 251 #define CFG_PROMPT_HUSH_PS2 "> " 252 #endif 253 254 /* pass open firmware flat tree */ 255 #define CONFIG_OF_LIBFDT 1 256 #define CONFIG_OF_BOARD_SETUP 1 257 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 258 259 /* I2C */ 260 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 261 #define CONFIG_HARD_I2C /* I2C with hardware support */ 262 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 263 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 264 #define CFG_I2C_EEPROM_ADDR 0x57 265 #define CFG_I2C_SLAVE 0x7F 266 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 267 #define CFG_I2C_OFFSET 0x3100 268 269 /* 270 * General PCI 271 * Memory space is mapped 1-1, but I/O space must start from 0. 272 */ 273 #define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 274 #define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 275 276 #define CFG_PCI1_MEM_BASE 0xc0000000 277 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 278 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 279 #define CFG_PCI1_IO_BASE 0x00000000 280 #define CFG_PCI1_IO_PHYS 0xe1000000 281 #define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */ 282 283 /* PCI view of System Memory */ 284 #define CFG_PCI_MEMORY_BUS 0x00000000 285 #define CFG_PCI_MEMORY_PHYS 0x00000000 286 #define CFG_PCI_MEMORY_SIZE 0x80000000 287 288 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 289 #define CFG_PCIE2_MEM_BASE 0x80000000 290 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE 291 #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 292 #define CFG_PCIE2_IO_BASE 0x00000000 293 #define CFG_PCIE2_IO_PHYS 0xe1010000 294 #define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */ 295 296 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 297 #define CFG_PCIE1_MEM_BASE 0xa0000000 298 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 299 #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 300 #define CFG_PCIE1_IO_BASE 0x00000000 301 #define CFG_PCIE1_IO_PHYS 0xe1020000 302 #define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */ 303 304 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 305 #define CFG_PCIE3_MEM_BASE 0xb0000000 306 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE 307 #define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 308 #define CFG_PCIE3_IO_BASE 0x00000000 309 #define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 310 #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ 311 #define CFG_PCIE3_MEM_BASE2 0xb0200000 312 #define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2 313 #define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 314 315 #if defined(CONFIG_PCI) 316 317 #define CONFIG_NET_MULTI 318 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 319 320 #undef CONFIG_EEPRO100 321 #undef CONFIG_TULIP 322 #define CONFIG_RTL8139 323 324 #ifdef CONFIG_RTL8139 325 /* This macro is used by RTL8139 but not defined in PPC architecture */ 326 #define KSEG1ADDR(x) (x) 327 #define _IO_BASE 0x00000000 328 #endif 329 330 #ifndef CONFIG_PCI_PNP 331 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE 332 #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE 333 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 334 #endif 335 336 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 337 #define CONFIG_DOS_PARTITION 338 #define CONFIG_SCSI_AHCI 339 340 #ifdef CONFIG_SCSI_AHCI 341 #define CONFIG_SATA_ULI5288 342 #define CFG_SCSI_MAX_SCSI_ID 4 343 #define CFG_SCSI_MAX_LUN 1 344 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 345 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 346 #endif /* SCSCI */ 347 348 #endif /* CONFIG_PCI */ 349 350 351 #if defined(CONFIG_TSEC_ENET) 352 353 #ifndef CONFIG_NET_MULTI 354 #define CONFIG_NET_MULTI 1 355 #endif 356 357 #define CONFIG_MII 1 /* MII PHY management */ 358 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 359 #define CONFIG_TSEC1 1 360 #define CONFIG_TSEC1_NAME "eTSEC1" 361 #define CONFIG_TSEC3 1 362 #define CONFIG_TSEC3_NAME "eTSEC3" 363 364 #define TSEC1_PHY_ADDR 0 365 #define TSEC3_PHY_ADDR 1 366 367 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 368 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 369 370 #define TSEC1_PHYIDX 0 371 #define TSEC3_PHYIDX 0 372 373 #define CONFIG_ETHPRIME "eTSEC1" 374 375 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 376 #endif /* CONFIG_TSEC_ENET */ 377 378 /* 379 * Environment 380 */ 381 #define CFG_ENV_IS_IN_FLASH 1 382 #if CFG_MONITOR_BASE > 0xfff80000 383 #define CFG_ENV_ADDR 0xfff80000 384 #else 385 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 386 #endif 387 #define CFG_ENV_SIZE 0x2000 388 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 389 390 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 391 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 392 393 /* 394 * BOOTP options 395 */ 396 #define CONFIG_BOOTP_BOOTFILESIZE 397 #define CONFIG_BOOTP_BOOTPATH 398 #define CONFIG_BOOTP_GATEWAY 399 #define CONFIG_BOOTP_HOSTNAME 400 401 402 /* 403 * Command line configuration. 404 */ 405 #include <config_cmd_default.h> 406 407 #define CONFIG_CMD_PING 408 #define CONFIG_CMD_I2C 409 #define CONFIG_CMD_MII 410 #define CONFIG_CMD_ELF 411 412 #if defined(CONFIG_PCI) 413 #define CONFIG_CMD_PCI 414 #define CONFIG_CMD_BEDBUG 415 #define CONFIG_CMD_NET 416 #define CONFIG_CMD_SCSI 417 #define CONFIG_CMD_EXT2 418 #endif 419 420 421 #undef CONFIG_WATCHDOG /* watchdog disabled */ 422 423 /* 424 * Miscellaneous configurable options 425 */ 426 #define CFG_LONGHELP /* undef to save memory */ 427 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 428 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 429 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 430 #if defined(CONFIG_CMD_KGDB) 431 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 432 #else 433 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 434 #endif 435 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 436 #define CFG_MAXARGS 16 /* max number of command args */ 437 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 438 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 439 440 /* 441 * For booting Linux, the board info and command line data 442 * have to be in the first 8 MB of memory, since this is 443 * the maximum mapped by the Linux kernel during initialization. 444 */ 445 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 446 447 /* 448 * Internal Definitions 449 * 450 * Boot Flags 451 */ 452 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 453 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 454 455 #if defined(CONFIG_CMD_KGDB) 456 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 457 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 458 #endif 459 460 /* 461 * Environment Configuration 462 */ 463 464 /* The mac addresses for all ethernet interface */ 465 #if defined(CONFIG_TSEC_ENET) 466 #define CONFIG_HAS_ETH0 467 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 468 #define CONFIG_HAS_ETH1 469 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 470 #endif 471 472 #define CONFIG_IPADDR 192.168.1.251 473 474 #define CONFIG_HOSTNAME 8544ds_unknown 475 #define CONFIG_ROOTPATH /nfs/mpc85xx 476 #define CONFIG_BOOTFILE 8544ds/uImage.uboot 477 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 478 479 #define CONFIG_SERVERIP 192.168.1.1 480 #define CONFIG_GATEWAYIP 192.168.1.1 481 #define CONFIG_NETMASK 255.255.0.0 482 483 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 484 485 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 486 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 487 488 #define CONFIG_BAUDRATE 115200 489 490 #define CONFIG_EXTRA_ENV_SETTINGS \ 491 "netdev=eth0\0" \ 492 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 493 "tftpflash=tftpboot $loadaddr $uboot; " \ 494 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 495 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 496 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 497 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 498 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 499 "consoledev=ttyS0\0" \ 500 "ramdiskaddr=2000000\0" \ 501 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 502 "fdtaddr=c00000\0" \ 503 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 504 "bdev=sda3\0" 505 506 #define CONFIG_NFSBOOTCOMMAND \ 507 "setenv bootargs root=/dev/nfs rw " \ 508 "nfsroot=$serverip:$rootpath " \ 509 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 510 "console=$consoledev,$baudrate $othbootargs;" \ 511 "tftp $loadaddr $bootfile;" \ 512 "tftp $fdtaddr $fdtfile;" \ 513 "bootm $loadaddr - $fdtaddr" 514 515 #define CONFIG_RAMBOOTCOMMAND \ 516 "setenv bootargs root=/dev/ram rw " \ 517 "console=$consoledev,$baudrate $othbootargs;" \ 518 "tftp $ramdiskaddr $ramdiskfile;" \ 519 "tftp $loadaddr $bootfile;" \ 520 "tftp $fdtaddr $fdtfile;" \ 521 "bootm $loadaddr $ramdiskaddr $fdtaddr" 522 523 #define CONFIG_BOOTCOMMAND \ 524 "setenv bootargs root=/dev/$bdev rw " \ 525 "console=$consoledev,$baudrate $othbootargs;" \ 526 "tftp $loadaddr $bootfile;" \ 527 "tftp $fdtaddr $fdtfile;" \ 528 "bootm $loadaddr - $fdtaddr" 529 530 #endif /* __CONFIG_H */ 531