1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8544ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_BOOKE 1 /* BOOKE */ 16 #define CONFIG_E500 1 /* BOOKE e500 family */ 17 #define CONFIG_MPC8544 1 18 #define CONFIG_MPC8544DS 1 19 20 #ifndef CONFIG_SYS_TEXT_BASE 21 #define CONFIG_SYS_TEXT_BASE 0xfff80000 22 #endif 23 24 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 25 #define CONFIG_PCI1 1 /* PCI controller 1 */ 26 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 27 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 28 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 29 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 30 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 31 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 32 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 33 34 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 35 36 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 37 #define CONFIG_ENV_OVERWRITE 38 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 39 40 #ifndef __ASSEMBLY__ 41 extern unsigned long get_board_sys_clk(unsigned long dummy); 42 #endif 43 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 44 45 /* 46 * These can be toggled for performance analysis, otherwise use default. 47 */ 48 #define CONFIG_L2_CACHE /* toggle L2 cache */ 49 #define CONFIG_BTB /* toggle branch predition */ 50 51 /* 52 * Only possible on E500 Version 2 or newer cores. 53 */ 54 #define CONFIG_ENABLE_36BIT_PHYS 1 55 56 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 57 #define CONFIG_SYS_MEMTEST_END 0x00400000 58 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 59 60 #define CONFIG_SYS_CCSRBAR 0xe0000000 61 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 62 63 /* DDR Setup */ 64 #define CONFIG_SYS_FSL_DDR2 65 #undef CONFIG_FSL_DDR_INTERACTIVE 66 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 67 #define CONFIG_DDR_SPD 68 69 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 70 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 71 72 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 73 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 74 #define CONFIG_VERY_BIG_RAM 75 76 #define CONFIG_NUM_DDR_CONTROLLERS 1 77 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 78 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 79 80 /* I2C addresses of SPD EEPROMs */ 81 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 82 83 /* Make sure required options are set */ 84 #ifndef CONFIG_SPD_EEPROM 85 #error ("CONFIG_SPD_EEPROM is required") 86 #endif 87 88 #undef CONFIG_CLOCKS_IN_MHZ 89 90 /* 91 * Memory map 92 * 93 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 94 * 95 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 96 * 97 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 98 * 99 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 100 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 101 * 102 * Localbus cacheable 103 * 104 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 105 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 106 * 107 * Localbus non-cacheable 108 * 109 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 110 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 111 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 112 * 113 */ 114 115 /* 116 * Local Bus Definitions 117 */ 118 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 119 120 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 121 122 #define CONFIG_SYS_BR0_PRELIM 0xff801001 123 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 124 125 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 126 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 127 128 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 129 130 #define CONFIG_SYS_FLASH_QUIET_TEST 131 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 132 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 133 #undef CONFIG_SYS_FLASH_CHECKSUM 134 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 135 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 136 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 137 138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 139 140 #define CONFIG_FLASH_CFI_DRIVER 141 #define CONFIG_SYS_FLASH_CFI 142 #define CONFIG_SYS_FLASH_EMPTY_INFO 143 144 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 145 146 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 147 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 148 149 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 150 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 151 152 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 153 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 154 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 155 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 156 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 157 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 158 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 159 * register */ 160 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 161 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 162 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 163 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 164 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 165 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 166 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 167 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 168 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 169 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 170 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 171 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 172 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 173 #define PIXIS_VSPEED2_TSEC1SER 0x2 174 #define PIXIS_VSPEED2_TSEC3SER 0x1 175 #define PIXIS_VCFGEN1_TSEC1SER 0x20 176 #define PIXIS_VCFGEN1_TSEC3SER 0x40 177 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 178 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 179 180 181 #define CONFIG_SYS_INIT_RAM_LOCK 1 182 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 183 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 184 185 186 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 187 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 188 189 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 190 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 191 192 /* Serial Port - controlled on board with jumper J8 193 * open - index 2 194 * shorted - index 1 195 */ 196 #define CONFIG_CONS_INDEX 1 197 #define CONFIG_SYS_NS16550 198 #define CONFIG_SYS_NS16550_SERIAL 199 #define CONFIG_SYS_NS16550_REG_SIZE 1 200 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 201 202 #define CONFIG_SYS_BAUDRATE_TABLE \ 203 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 204 205 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 206 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 207 208 /* Use the HUSH parser */ 209 #define CONFIG_SYS_HUSH_PARSER 210 211 /* pass open firmware flat tree */ 212 #define CONFIG_OF_LIBFDT 1 213 #define CONFIG_OF_BOARD_SETUP 1 214 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 215 216 /* I2C */ 217 #define CONFIG_SYS_I2C 218 #define CONFIG_SYS_I2C_FSL 219 #define CONFIG_SYS_FSL_I2C_SPEED 400000 220 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 221 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 222 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 223 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 224 225 /* 226 * General PCI 227 * Memory space is mapped 1-1, but I/O space must start from 0. 228 */ 229 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 230 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 231 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 232 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 233 234 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 235 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 236 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 237 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 238 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 239 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 240 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 241 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 242 243 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 244 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 245 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 246 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 247 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 248 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 249 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 250 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 251 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 252 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 253 254 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 255 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 256 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 257 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 258 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 259 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 260 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 261 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 262 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 263 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 264 265 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 266 #define CONFIG_SYS_PCIE3_NAME "ULI" 267 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 268 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 269 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 270 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 271 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 272 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 273 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 274 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 275 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 276 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 277 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 278 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 279 280 #if defined(CONFIG_PCI) 281 282 /*PCIE video card used*/ 283 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 284 285 /*PCI video card used*/ 286 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 287 288 /* video */ 289 #define CONFIG_VIDEO 290 291 #if defined(CONFIG_VIDEO) 292 #define CONFIG_BIOSEMU 293 #define CONFIG_CFB_CONSOLE 294 #define CONFIG_VIDEO_SW_CURSOR 295 #define CONFIG_VGA_AS_SINGLE_DEVICE 296 #define CONFIG_ATI_RADEON_FB 297 #define CONFIG_VIDEO_LOGO 298 /*#define CONFIG_CONSOLE_CURSOR*/ 299 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 300 #endif 301 302 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 303 304 #undef CONFIG_EEPRO100 305 #undef CONFIG_TULIP 306 #define CONFIG_RTL8139 307 308 #ifndef CONFIG_PCI_PNP 309 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 310 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 311 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 312 #endif 313 314 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 315 #define CONFIG_DOS_PARTITION 316 #define CONFIG_SCSI_AHCI 317 318 #ifdef CONFIG_SCSI_AHCI 319 #define CONFIG_LIBATA 320 #define CONFIG_SATA_ULI5288 321 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 322 #define CONFIG_SYS_SCSI_MAX_LUN 1 323 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 324 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 325 #endif /* SCSCI */ 326 327 #endif /* CONFIG_PCI */ 328 329 330 #if defined(CONFIG_TSEC_ENET) 331 332 #define CONFIG_MII 1 /* MII PHY management */ 333 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 334 #define CONFIG_TSEC1 1 335 #define CONFIG_TSEC1_NAME "eTSEC1" 336 #define CONFIG_TSEC3 1 337 #define CONFIG_TSEC3_NAME "eTSEC3" 338 339 #define CONFIG_PIXIS_SGMII_CMD 340 #define CONFIG_FSL_SGMII_RISER 1 341 #define SGMII_RISER_PHY_OFFSET 0x1c 342 343 #define TSEC1_PHY_ADDR 0 344 #define TSEC3_PHY_ADDR 1 345 346 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 347 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 348 349 #define TSEC1_PHYIDX 0 350 #define TSEC3_PHYIDX 0 351 352 #define CONFIG_ETHPRIME "eTSEC1" 353 354 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 355 #endif /* CONFIG_TSEC_ENET */ 356 357 /* 358 * Environment 359 */ 360 #define CONFIG_ENV_IS_IN_FLASH 1 361 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 362 #define CONFIG_ENV_ADDR 0xfff80000 363 #else 364 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) 365 #endif 366 #define CONFIG_ENV_SIZE 0x2000 367 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 368 369 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 370 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 371 372 /* 373 * BOOTP options 374 */ 375 #define CONFIG_BOOTP_BOOTFILESIZE 376 #define CONFIG_BOOTP_BOOTPATH 377 #define CONFIG_BOOTP_GATEWAY 378 #define CONFIG_BOOTP_HOSTNAME 379 380 381 /* 382 * Command line configuration. 383 */ 384 #define CONFIG_CMD_PING 385 #define CONFIG_CMD_I2C 386 #define CONFIG_CMD_MII 387 #define CONFIG_CMD_ELF 388 #define CONFIG_CMD_IRQ 389 #define CONFIG_CMD_REGINFO 390 391 #if defined(CONFIG_PCI) 392 #define CONFIG_CMD_PCI 393 #define CONFIG_CMD_SCSI 394 #define CONFIG_CMD_EXT2 395 #endif 396 397 /* 398 * USB 399 */ 400 #define CONFIG_USB_EHCI 401 402 #ifdef CONFIG_USB_EHCI 403 #define CONFIG_CMD_USB 404 #define CONFIG_USB_EHCI_PCI 405 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 406 #define CONFIG_USB_STORAGE 407 #define CONFIG_PCI_EHCI_DEVICE 0 408 #endif 409 410 #undef CONFIG_WATCHDOG /* watchdog disabled */ 411 412 /* 413 * Miscellaneous configurable options 414 */ 415 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 416 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 417 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 418 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 419 #if defined(CONFIG_CMD_KGDB) 420 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 421 #else 422 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 423 #endif 424 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 425 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 426 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 427 428 /* 429 * For booting Linux, the board info and command line data 430 * have to be in the first 64 MB of memory, since this is 431 * the maximum mapped by the Linux kernel during initialization. 432 */ 433 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 434 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 435 436 #if defined(CONFIG_CMD_KGDB) 437 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 438 #endif 439 440 /* 441 * Environment Configuration 442 */ 443 444 /* The mac addresses for all ethernet interface */ 445 #if defined(CONFIG_TSEC_ENET) 446 #define CONFIG_HAS_ETH0 447 #define CONFIG_HAS_ETH1 448 #endif 449 450 #define CONFIG_IPADDR 192.168.1.251 451 452 #define CONFIG_HOSTNAME 8544ds_unknown 453 #define CONFIG_ROOTPATH "/nfs/mpc85xx" 454 #define CONFIG_BOOTFILE "8544ds/uImage.uboot" 455 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 456 457 #define CONFIG_SERVERIP 192.168.1.1 458 #define CONFIG_GATEWAYIP 192.168.1.1 459 #define CONFIG_NETMASK 255.255.0.0 460 461 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 462 463 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 464 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 465 466 #define CONFIG_BAUDRATE 115200 467 468 #define CONFIG_EXTRA_ENV_SETTINGS \ 469 "netdev=eth0\0" \ 470 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 471 "tftpflash=tftpboot $loadaddr $uboot; " \ 472 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 473 " +$filesize; " \ 474 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 475 " +$filesize; " \ 476 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 477 " $filesize; " \ 478 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 479 " +$filesize; " \ 480 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 481 " $filesize\0" \ 482 "consoledev=ttyS0\0" \ 483 "ramdiskaddr=2000000\0" \ 484 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 485 "fdtaddr=c00000\0" \ 486 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 487 "bdev=sda3\0" 488 489 #define CONFIG_NFSBOOTCOMMAND \ 490 "setenv bootargs root=/dev/nfs rw " \ 491 "nfsroot=$serverip:$rootpath " \ 492 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 493 "console=$consoledev,$baudrate $othbootargs;" \ 494 "tftp $loadaddr $bootfile;" \ 495 "tftp $fdtaddr $fdtfile;" \ 496 "bootm $loadaddr - $fdtaddr" 497 498 #define CONFIG_RAMBOOTCOMMAND \ 499 "setenv bootargs root=/dev/ram rw " \ 500 "console=$consoledev,$baudrate $othbootargs;" \ 501 "tftp $ramdiskaddr $ramdiskfile;" \ 502 "tftp $loadaddr $bootfile;" \ 503 "tftp $fdtaddr $fdtfile;" \ 504 "bootm $loadaddr $ramdiskaddr $fdtaddr" 505 506 #define CONFIG_BOOTCOMMAND \ 507 "setenv bootargs root=/dev/$bdev rw " \ 508 "console=$consoledev,$baudrate $othbootargs;" \ 509 "tftp $loadaddr $bootfile;" \ 510 "tftp $fdtaddr $fdtfile;" \ 511 "bootm $loadaddr - $fdtaddr" 512 513 #endif /* __CONFIG_H */ 514