1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8544ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 /* High Level Configuration Options */ 18 #define CONFIG_BOOKE 1 /* BOOKE */ 19 #define CONFIG_E500 1 /* BOOKE e500 family */ 20 #define CONFIG_MPC8544 1 21 #define CONFIG_MPC8544DS 1 22 23 #ifndef CONFIG_SYS_TEXT_BASE 24 #define CONFIG_SYS_TEXT_BASE 0xfff80000 25 #endif 26 27 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 28 #define CONFIG_PCI1 1 /* PCI controller 1 */ 29 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 30 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 31 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 32 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 33 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 34 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 35 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 36 37 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 38 39 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 40 #define CONFIG_ENV_OVERWRITE 41 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 42 43 #ifndef __ASSEMBLY__ 44 extern unsigned long get_board_sys_clk(unsigned long dummy); 45 #endif 46 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 47 48 /* 49 * These can be toggled for performance analysis, otherwise use default. 50 */ 51 #define CONFIG_L2_CACHE /* toggle L2 cache */ 52 #define CONFIG_BTB /* toggle branch predition */ 53 54 /* 55 * Only possible on E500 Version 2 or newer cores. 56 */ 57 #define CONFIG_ENABLE_36BIT_PHYS 1 58 59 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 60 #define CONFIG_SYS_MEMTEST_END 0x00400000 61 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 62 63 #define CONFIG_SYS_CCSRBAR 0xe0000000 64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 65 66 /* DDR Setup */ 67 #define CONFIG_SYS_FSL_DDR2 68 #undef CONFIG_FSL_DDR_INTERACTIVE 69 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 70 #define CONFIG_DDR_SPD 71 72 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 73 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 74 75 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 76 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 77 #define CONFIG_VERY_BIG_RAM 78 79 #define CONFIG_NUM_DDR_CONTROLLERS 1 80 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 81 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 82 83 /* I2C addresses of SPD EEPROMs */ 84 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 85 86 /* Make sure required options are set */ 87 #ifndef CONFIG_SPD_EEPROM 88 #error ("CONFIG_SPD_EEPROM is required") 89 #endif 90 91 #undef CONFIG_CLOCKS_IN_MHZ 92 93 /* 94 * Memory map 95 * 96 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 97 * 98 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 99 * 100 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 101 * 102 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 103 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 104 * 105 * Localbus cacheable 106 * 107 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 108 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 109 * 110 * Localbus non-cacheable 111 * 112 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 113 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 114 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 115 * 116 */ 117 118 /* 119 * Local Bus Definitions 120 */ 121 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 122 123 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 124 125 #define CONFIG_SYS_BR0_PRELIM 0xff801001 126 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 127 128 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 129 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 130 131 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 132 133 #define CONFIG_SYS_FLASH_QUIET_TEST 134 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 135 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 136 #undef CONFIG_SYS_FLASH_CHECKSUM 137 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 138 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 139 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 140 141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 142 143 #define CONFIG_FLASH_CFI_DRIVER 144 #define CONFIG_SYS_FLASH_CFI 145 #define CONFIG_SYS_FLASH_EMPTY_INFO 146 147 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 148 149 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 150 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 151 152 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 153 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 154 155 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 156 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 157 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 158 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 159 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 160 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 161 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 162 * register */ 163 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 164 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 165 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 166 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 167 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 168 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 169 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 170 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 171 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 172 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 173 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 174 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 175 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 176 #define PIXIS_VSPEED2_TSEC1SER 0x2 177 #define PIXIS_VSPEED2_TSEC3SER 0x1 178 #define PIXIS_VCFGEN1_TSEC1SER 0x20 179 #define PIXIS_VCFGEN1_TSEC3SER 0x40 180 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 181 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 182 183 184 #define CONFIG_SYS_INIT_RAM_LOCK 1 185 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 186 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 187 188 189 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 190 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 191 192 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 193 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 194 195 /* Serial Port - controlled on board with jumper J8 196 * open - index 2 197 * shorted - index 1 198 */ 199 #define CONFIG_CONS_INDEX 1 200 #define CONFIG_SYS_NS16550 201 #define CONFIG_SYS_NS16550_SERIAL 202 #define CONFIG_SYS_NS16550_REG_SIZE 1 203 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 204 205 #define CONFIG_SYS_BAUDRATE_TABLE \ 206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 207 208 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 209 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 210 211 /* Use the HUSH parser */ 212 #define CONFIG_SYS_HUSH_PARSER 213 214 /* pass open firmware flat tree */ 215 #define CONFIG_OF_LIBFDT 1 216 #define CONFIG_OF_BOARD_SETUP 1 217 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 218 219 /* I2C */ 220 #define CONFIG_SYS_I2C 221 #define CONFIG_SYS_I2C_FSL 222 #define CONFIG_SYS_FSL_I2C_SPEED 400000 223 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 224 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 225 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 226 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 227 228 /* 229 * General PCI 230 * Memory space is mapped 1-1, but I/O space must start from 0. 231 */ 232 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 233 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 234 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 235 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 236 237 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 238 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 239 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 240 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 241 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 242 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 243 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 244 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 245 246 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 247 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 248 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 249 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 250 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 251 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 252 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 253 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 254 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 255 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 256 257 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 258 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 259 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 260 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 261 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 262 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 263 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 264 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 265 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 266 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 267 268 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 269 #define CONFIG_SYS_PCIE3_NAME "ULI" 270 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 271 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 272 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 273 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 274 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 275 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 276 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 277 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 278 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 279 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 280 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 281 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 282 283 #if defined(CONFIG_PCI) 284 285 /*PCIE video card used*/ 286 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 287 288 /*PCI video card used*/ 289 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 290 291 /* video */ 292 #define CONFIG_VIDEO 293 294 #if defined(CONFIG_VIDEO) 295 #define CONFIG_BIOSEMU 296 #define CONFIG_CFB_CONSOLE 297 #define CONFIG_VIDEO_SW_CURSOR 298 #define CONFIG_VGA_AS_SINGLE_DEVICE 299 #define CONFIG_ATI_RADEON_FB 300 #define CONFIG_VIDEO_LOGO 301 /*#define CONFIG_CONSOLE_CURSOR*/ 302 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 303 #endif 304 305 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 306 307 #undef CONFIG_EEPRO100 308 #undef CONFIG_TULIP 309 #define CONFIG_RTL8139 310 311 #ifndef CONFIG_PCI_PNP 312 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 313 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 314 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 315 #endif 316 317 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 318 #define CONFIG_DOS_PARTITION 319 #define CONFIG_SCSI_AHCI 320 321 #ifdef CONFIG_SCSI_AHCI 322 #define CONFIG_LIBATA 323 #define CONFIG_SATA_ULI5288 324 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 325 #define CONFIG_SYS_SCSI_MAX_LUN 1 326 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 327 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 328 #endif /* SCSCI */ 329 330 #endif /* CONFIG_PCI */ 331 332 333 #if defined(CONFIG_TSEC_ENET) 334 335 #define CONFIG_MII 1 /* MII PHY management */ 336 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 337 #define CONFIG_TSEC1 1 338 #define CONFIG_TSEC1_NAME "eTSEC1" 339 #define CONFIG_TSEC3 1 340 #define CONFIG_TSEC3_NAME "eTSEC3" 341 342 #define CONFIG_PIXIS_SGMII_CMD 343 #define CONFIG_FSL_SGMII_RISER 1 344 #define SGMII_RISER_PHY_OFFSET 0x1c 345 346 #define TSEC1_PHY_ADDR 0 347 #define TSEC3_PHY_ADDR 1 348 349 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 350 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 351 352 #define TSEC1_PHYIDX 0 353 #define TSEC3_PHYIDX 0 354 355 #define CONFIG_ETHPRIME "eTSEC1" 356 357 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 358 #endif /* CONFIG_TSEC_ENET */ 359 360 /* 361 * Environment 362 */ 363 #define CONFIG_ENV_IS_IN_FLASH 1 364 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 365 #define CONFIG_ENV_ADDR 0xfff80000 366 #else 367 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) 368 #endif 369 #define CONFIG_ENV_SIZE 0x2000 370 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 371 372 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 373 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 374 375 /* 376 * BOOTP options 377 */ 378 #define CONFIG_BOOTP_BOOTFILESIZE 379 #define CONFIG_BOOTP_BOOTPATH 380 #define CONFIG_BOOTP_GATEWAY 381 #define CONFIG_BOOTP_HOSTNAME 382 383 384 /* 385 * Command line configuration. 386 */ 387 #define CONFIG_CMD_PING 388 #define CONFIG_CMD_I2C 389 #define CONFIG_CMD_MII 390 #define CONFIG_CMD_IRQ 391 #define CONFIG_CMD_REGINFO 392 393 #if defined(CONFIG_PCI) 394 #define CONFIG_CMD_PCI 395 #define CONFIG_CMD_SCSI 396 #define CONFIG_CMD_EXT2 397 #endif 398 399 /* 400 * USB 401 */ 402 #define CONFIG_USB_EHCI 403 404 #ifdef CONFIG_USB_EHCI 405 #define CONFIG_CMD_USB 406 #define CONFIG_USB_EHCI_PCI 407 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 408 #define CONFIG_USB_STORAGE 409 #define CONFIG_PCI_EHCI_DEVICE 0 410 #endif 411 412 #undef CONFIG_WATCHDOG /* watchdog disabled */ 413 414 /* 415 * Miscellaneous configurable options 416 */ 417 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 418 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 419 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 420 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 421 #if defined(CONFIG_CMD_KGDB) 422 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 423 #else 424 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 425 #endif 426 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 427 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 428 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 429 430 /* 431 * For booting Linux, the board info and command line data 432 * have to be in the first 64 MB of memory, since this is 433 * the maximum mapped by the Linux kernel during initialization. 434 */ 435 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 436 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 437 438 #if defined(CONFIG_CMD_KGDB) 439 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 440 #endif 441 442 /* 443 * Environment Configuration 444 */ 445 446 /* The mac addresses for all ethernet interface */ 447 #if defined(CONFIG_TSEC_ENET) 448 #define CONFIG_HAS_ETH0 449 #define CONFIG_HAS_ETH1 450 #endif 451 452 #define CONFIG_IPADDR 192.168.1.251 453 454 #define CONFIG_HOSTNAME 8544ds_unknown 455 #define CONFIG_ROOTPATH "/nfs/mpc85xx" 456 #define CONFIG_BOOTFILE "8544ds/uImage.uboot" 457 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 458 459 #define CONFIG_SERVERIP 192.168.1.1 460 #define CONFIG_GATEWAYIP 192.168.1.1 461 #define CONFIG_NETMASK 255.255.0.0 462 463 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 464 465 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 466 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 467 468 #define CONFIG_BAUDRATE 115200 469 470 #define CONFIG_EXTRA_ENV_SETTINGS \ 471 "netdev=eth0\0" \ 472 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 473 "tftpflash=tftpboot $loadaddr $uboot; " \ 474 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 475 " +$filesize; " \ 476 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 477 " +$filesize; " \ 478 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 479 " $filesize; " \ 480 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 481 " +$filesize; " \ 482 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 483 " $filesize\0" \ 484 "consoledev=ttyS0\0" \ 485 "ramdiskaddr=2000000\0" \ 486 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 487 "fdtaddr=c00000\0" \ 488 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 489 "bdev=sda3\0" 490 491 #define CONFIG_NFSBOOTCOMMAND \ 492 "setenv bootargs root=/dev/nfs rw " \ 493 "nfsroot=$serverip:$rootpath " \ 494 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 495 "console=$consoledev,$baudrate $othbootargs;" \ 496 "tftp $loadaddr $bootfile;" \ 497 "tftp $fdtaddr $fdtfile;" \ 498 "bootm $loadaddr - $fdtaddr" 499 500 #define CONFIG_RAMBOOTCOMMAND \ 501 "setenv bootargs root=/dev/ram rw " \ 502 "console=$consoledev,$baudrate $othbootargs;" \ 503 "tftp $ramdiskaddr $ramdiskfile;" \ 504 "tftp $loadaddr $bootfile;" \ 505 "tftp $fdtaddr $fdtfile;" \ 506 "bootm $loadaddr $ramdiskaddr $fdtaddr" 507 508 #define CONFIG_BOOTCOMMAND \ 509 "setenv bootargs root=/dev/$bdev rw " \ 510 "console=$consoledev,$baudrate $othbootargs;" \ 511 "tftp $loadaddr $bootfile;" \ 512 "tftp $fdtaddr $fdtfile;" \ 513 "bootm $loadaddr - $fdtaddr" 514 515 #endif /* __CONFIG_H */ 516