1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * mpc8544ds board configuration file 8 * 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_PCI1 1 /* PCI controller 1 */ 14 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 15 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 16 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 17 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 18 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 19 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 20 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 21 22 #define CONFIG_ENV_OVERWRITE 23 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 24 25 #ifndef __ASSEMBLY__ 26 extern unsigned long get_board_sys_clk(unsigned long dummy); 27 #endif 28 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 29 30 /* 31 * These can be toggled for performance analysis, otherwise use default. 32 */ 33 #define CONFIG_L2_CACHE /* toggle L2 cache */ 34 #define CONFIG_BTB /* toggle branch predition */ 35 36 /* 37 * Only possible on E500 Version 2 or newer cores. 38 */ 39 #define CONFIG_ENABLE_36BIT_PHYS 1 40 41 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 42 #define CONFIG_SYS_MEMTEST_END 0x00400000 43 44 #define CONFIG_SYS_CCSRBAR 0xe0000000 45 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 46 47 /* DDR Setup */ 48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 49 #define CONFIG_DDR_SPD 50 51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 53 54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 56 #define CONFIG_VERY_BIG_RAM 57 58 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 59 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 60 61 /* I2C addresses of SPD EEPROMs */ 62 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 63 64 /* Make sure required options are set */ 65 #ifndef CONFIG_SPD_EEPROM 66 #error ("CONFIG_SPD_EEPROM is required") 67 #endif 68 69 #undef CONFIG_CLOCKS_IN_MHZ 70 71 /* 72 * Memory map 73 * 74 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 75 * 76 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 77 * 78 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 79 * 80 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 81 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 82 * 83 * Localbus cacheable 84 * 85 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 86 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 87 * 88 * Localbus non-cacheable 89 * 90 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 91 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 92 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 93 * 94 */ 95 96 /* 97 * Local Bus Definitions 98 */ 99 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 100 101 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 102 103 #define CONFIG_SYS_BR0_PRELIM 0xff801001 104 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 105 106 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 107 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 108 109 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 110 111 #define CONFIG_SYS_FLASH_QUIET_TEST 112 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 113 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 114 #undef CONFIG_SYS_FLASH_CHECKSUM 115 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 116 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 117 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 118 119 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 120 121 #define CONFIG_SYS_FLASH_EMPTY_INFO 122 123 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 124 125 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 126 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 127 128 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 129 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 130 131 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 132 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 133 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 134 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 135 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 136 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 137 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 138 * register */ 139 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 140 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 141 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 142 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 143 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 144 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 145 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 146 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 147 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 148 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 149 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 150 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 151 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 152 #define PIXIS_VSPEED2_TSEC1SER 0x2 153 #define PIXIS_VSPEED2_TSEC3SER 0x1 154 #define PIXIS_VCFGEN1_TSEC1SER 0x20 155 #define PIXIS_VCFGEN1_TSEC3SER 0x40 156 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 157 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 158 159 #define CONFIG_SYS_INIT_RAM_LOCK 1 160 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 161 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 162 163 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 164 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 165 166 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 167 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 168 169 /* Serial Port - controlled on board with jumper J8 170 * open - index 2 171 * shorted - index 1 172 */ 173 #define CONFIG_SYS_NS16550_SERIAL 174 #define CONFIG_SYS_NS16550_REG_SIZE 1 175 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 176 177 #define CONFIG_SYS_BAUDRATE_TABLE \ 178 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 179 180 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 181 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 182 183 /* I2C */ 184 #define CONFIG_SYS_I2C 185 #define CONFIG_SYS_I2C_FSL 186 #define CONFIG_SYS_FSL_I2C_SPEED 400000 187 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 188 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 189 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 190 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 191 192 /* 193 * General PCI 194 * Memory space is mapped 1-1, but I/O space must start from 0. 195 */ 196 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 197 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 198 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 199 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 200 201 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 202 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 203 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 204 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 205 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 206 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 207 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 208 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 209 210 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 211 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 212 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 213 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 214 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 215 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 216 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 217 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 218 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 219 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 220 221 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 222 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 223 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 224 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 225 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 226 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 227 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 228 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 229 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 230 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 231 232 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 233 #define CONFIG_SYS_PCIE3_NAME "ULI" 234 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 235 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 236 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 237 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 238 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 239 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 240 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 241 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 242 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 243 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 244 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 245 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 246 247 #if defined(CONFIG_PCI) 248 249 /*PCIE video card used*/ 250 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 251 252 /*PCI video card used*/ 253 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 254 255 /* video */ 256 257 #if defined(CONFIG_VIDEO) 258 #define CONFIG_BIOSEMU 259 #define CONFIG_ATI_RADEON_FB 260 #define CONFIG_VIDEO_LOGO 261 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 262 #endif 263 264 #undef CONFIG_EEPRO100 265 #undef CONFIG_TULIP 266 267 #ifndef CONFIG_PCI_PNP 268 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 269 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 270 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 271 #endif 272 273 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 274 275 #ifdef CONFIG_SCSI_AHCI 276 #define CONFIG_SATA_ULI5288 277 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 278 #define CONFIG_SYS_SCSI_MAX_LUN 1 279 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 280 #endif /* CONFIG_SCSI_AHCI */ 281 282 #endif /* CONFIG_PCI */ 283 284 #if defined(CONFIG_TSEC_ENET) 285 286 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 287 #define CONFIG_TSEC1 1 288 #define CONFIG_TSEC1_NAME "eTSEC1" 289 #define CONFIG_TSEC3 1 290 #define CONFIG_TSEC3_NAME "eTSEC3" 291 292 #define CONFIG_PIXIS_SGMII_CMD 293 #define CONFIG_FSL_SGMII_RISER 1 294 #define SGMII_RISER_PHY_OFFSET 0x1c 295 296 #define TSEC1_PHY_ADDR 0 297 #define TSEC3_PHY_ADDR 1 298 299 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 300 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 301 302 #define TSEC1_PHYIDX 0 303 #define TSEC3_PHYIDX 0 304 305 #define CONFIG_ETHPRIME "eTSEC1" 306 #endif /* CONFIG_TSEC_ENET */ 307 308 /* 309 * Environment 310 */ 311 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 312 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 313 #define CONFIG_ENV_ADDR 0xfff80000 314 #else 315 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 316 #endif 317 #define CONFIG_ENV_SIZE 0x2000 318 319 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 320 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 321 322 /* 323 * BOOTP options 324 */ 325 #define CONFIG_BOOTP_BOOTFILESIZE 326 327 /* 328 * USB 329 */ 330 331 #ifdef CONFIG_USB_EHCI_HCD 332 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 333 #define CONFIG_PCI_EHCI_DEVICE 0 334 #endif 335 336 #undef CONFIG_WATCHDOG /* watchdog disabled */ 337 338 /* 339 * Miscellaneous configurable options 340 */ 341 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 342 343 /* 344 * For booting Linux, the board info and command line data 345 * have to be in the first 64 MB of memory, since this is 346 * the maximum mapped by the Linux kernel during initialization. 347 */ 348 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 349 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 350 351 #if defined(CONFIG_CMD_KGDB) 352 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 353 #endif 354 355 /* 356 * Environment Configuration 357 */ 358 359 /* The mac addresses for all ethernet interface */ 360 #if defined(CONFIG_TSEC_ENET) 361 #define CONFIG_HAS_ETH0 362 #define CONFIG_HAS_ETH1 363 #endif 364 365 #define CONFIG_IPADDR 192.168.1.251 366 367 #define CONFIG_HOSTNAME "8544ds_unknown" 368 #define CONFIG_ROOTPATH "/nfs/mpc85xx" 369 #define CONFIG_BOOTFILE "8544ds/uImage.uboot" 370 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 371 372 #define CONFIG_SERVERIP 192.168.1.1 373 #define CONFIG_GATEWAYIP 192.168.1.1 374 #define CONFIG_NETMASK 255.255.0.0 375 376 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 377 378 #define CONFIG_EXTRA_ENV_SETTINGS \ 379 "netdev=eth0\0" \ 380 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 381 "tftpflash=tftpboot $loadaddr $uboot; " \ 382 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 383 " +$filesize; " \ 384 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 385 " +$filesize; " \ 386 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 387 " $filesize; " \ 388 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 389 " +$filesize; " \ 390 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 391 " $filesize\0" \ 392 "consoledev=ttyS0\0" \ 393 "ramdiskaddr=2000000\0" \ 394 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 395 "fdtaddr=1e00000\0" \ 396 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 397 "bdev=sda3\0" 398 399 #define CONFIG_NFSBOOTCOMMAND \ 400 "setenv bootargs root=/dev/nfs rw " \ 401 "nfsroot=$serverip:$rootpath " \ 402 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 403 "console=$consoledev,$baudrate $othbootargs;" \ 404 "tftp $loadaddr $bootfile;" \ 405 "tftp $fdtaddr $fdtfile;" \ 406 "bootm $loadaddr - $fdtaddr" 407 408 #define CONFIG_RAMBOOTCOMMAND \ 409 "setenv bootargs root=/dev/ram rw " \ 410 "console=$consoledev,$baudrate $othbootargs;" \ 411 "tftp $ramdiskaddr $ramdiskfile;" \ 412 "tftp $loadaddr $bootfile;" \ 413 "tftp $fdtaddr $fdtfile;" \ 414 "bootm $loadaddr $ramdiskaddr $fdtaddr" 415 416 #define CONFIG_BOOTCOMMAND \ 417 "setenv bootargs root=/dev/$bdev rw " \ 418 "console=$consoledev,$baudrate $othbootargs;" \ 419 "tftp $loadaddr $bootfile;" \ 420 "tftp $fdtaddr $fdtfile;" \ 421 "bootm $loadaddr - $fdtaddr" 422 423 #endif /* __CONFIG_H */ 424