1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8544ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8544 1 35 #define CONFIG_MPC8544DS 1 36 37 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 38 #define CONFIG_PCI1 1 /* PCI controller 1 */ 39 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 40 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 41 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 44 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 45 46 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 47 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 48 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 52 53 #ifndef __ASSEMBLY__ 54 extern unsigned long get_board_sys_clk(unsigned long dummy); 55 #endif 56 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 57 58 /* 59 * These can be toggled for performance analysis, otherwise use default. 60 */ 61 #define CONFIG_L2_CACHE /* toggle L2 cache */ 62 #define CONFIG_BTB /* toggle branch predition */ 63 64 /* 65 * Only possible on E500 Version 2 or newer cores. 66 */ 67 #define CONFIG_ENABLE_36BIT_PHYS 1 68 69 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 70 #define CONFIG_SYS_MEMTEST_END 0x00400000 71 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 72 73 /* 74 * Base addresses -- Note these are effective addresses where the 75 * actual resources get mapped (not physical addresses) 76 */ 77 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 78 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 79 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 80 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 81 82 /* DDR Setup */ 83 #define CONFIG_FSL_DDR2 84 #undef CONFIG_FSL_DDR_INTERACTIVE 85 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 86 #define CONFIG_DDR_SPD 87 88 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 89 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 90 91 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 93 #define CONFIG_VERY_BIG_RAM 94 95 #define CONFIG_NUM_DDR_CONTROLLERS 1 96 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 97 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 98 99 /* I2C addresses of SPD EEPROMs */ 100 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 101 102 /* Make sure required options are set */ 103 #ifndef CONFIG_SPD_EEPROM 104 #error ("CONFIG_SPD_EEPROM is required") 105 #endif 106 107 #undef CONFIG_CLOCKS_IN_MHZ 108 109 /* 110 * Memory map 111 * 112 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 113 * 114 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 115 * 116 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 117 * 118 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 119 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 120 * 121 * Localbus cacheable 122 * 123 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 124 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 125 * 126 * Localbus non-cacheable 127 * 128 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 129 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 130 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 131 * 132 */ 133 134 /* 135 * Local Bus Definitions 136 */ 137 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 138 139 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 140 141 #define CONFIG_SYS_BR0_PRELIM 0xff801001 142 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 143 144 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 145 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 146 147 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 148 149 #define CONFIG_SYS_FLASH_QUIET_TEST 150 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 151 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 152 #undef CONFIG_SYS_FLASH_CHECKSUM 153 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 154 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 155 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 156 157 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 158 159 #define CONFIG_FLASH_CFI_DRIVER 160 #define CONFIG_SYS_FLASH_CFI 161 #define CONFIG_SYS_FLASH_EMPTY_INFO 162 163 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 164 165 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 166 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 167 168 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 169 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 170 171 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 172 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 173 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 174 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 175 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 176 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 177 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 178 * register */ 179 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 180 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 181 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 182 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 183 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 184 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 185 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 186 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 187 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 188 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 189 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 190 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 191 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 192 #define PIXIS_VSPEED2_TSEC1SER 0x2 193 #define PIXIS_VSPEED2_TSEC3SER 0x1 194 #define PIXIS_VCFGEN1_TSEC1SER 0x20 195 #define PIXIS_VCFGEN1_TSEC3SER 0x40 196 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 197 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 198 199 200 #define CONFIG_SYS_INIT_RAM_LOCK 1 201 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 202 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 203 204 205 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 206 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 207 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 208 209 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 210 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 211 212 /* Serial Port - controlled on board with jumper J8 213 * open - index 2 214 * shorted - index 1 215 */ 216 #define CONFIG_CONS_INDEX 1 217 #undef CONFIG_SERIAL_SOFTWARE_FIFO 218 #define CONFIG_SYS_NS16550 219 #define CONFIG_SYS_NS16550_SERIAL 220 #define CONFIG_SYS_NS16550_REG_SIZE 1 221 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 222 223 #define CONFIG_SYS_BAUDRATE_TABLE \ 224 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 225 226 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 227 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 228 229 /* Use the HUSH parser */ 230 #define CONFIG_SYS_HUSH_PARSER 231 #ifdef CONFIG_SYS_HUSH_PARSER 232 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 233 #endif 234 235 /* pass open firmware flat tree */ 236 #define CONFIG_OF_LIBFDT 1 237 #define CONFIG_OF_BOARD_SETUP 1 238 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 239 240 /* I2C */ 241 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 242 #define CONFIG_HARD_I2C /* I2C with hardware support */ 243 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 244 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 245 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 246 #define CONFIG_SYS_I2C_SLAVE 0x7F 247 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 248 #define CONFIG_SYS_I2C_OFFSET 0x3100 249 250 /* 251 * General PCI 252 * Memory space is mapped 1-1, but I/O space must start from 0. 253 */ 254 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 255 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 256 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 257 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 258 259 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 260 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 261 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 262 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 263 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 264 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 265 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 266 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 267 268 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 269 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 270 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 271 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 272 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 273 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 274 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 275 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 276 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 277 278 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 279 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 280 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 281 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 282 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 283 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 284 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 285 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 286 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 287 288 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 289 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 290 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 291 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 292 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 293 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 294 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 295 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 296 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 297 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 298 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 299 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 300 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 301 302 #if defined(CONFIG_PCI) 303 304 /*PCIE video card used*/ 305 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 306 307 /*PCI video card used*/ 308 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 309 310 /* video */ 311 #define CONFIG_VIDEO 312 313 #if defined(CONFIG_VIDEO) 314 #define CONFIG_BIOSEMU 315 #define CONFIG_CFB_CONSOLE 316 #define CONFIG_VIDEO_SW_CURSOR 317 #define CONFIG_VGA_AS_SINGLE_DEVICE 318 #define CONFIG_ATI_RADEON_FB 319 #define CONFIG_VIDEO_LOGO 320 /*#define CONFIG_CONSOLE_CURSOR*/ 321 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 322 #endif 323 324 #define CONFIG_NET_MULTI 325 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 326 327 #undef CONFIG_EEPRO100 328 #undef CONFIG_TULIP 329 #define CONFIG_RTL8139 330 331 #ifndef CONFIG_PCI_PNP 332 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 333 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 334 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 335 #endif 336 337 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 338 #define CONFIG_DOS_PARTITION 339 #define CONFIG_SCSI_AHCI 340 341 #ifdef CONFIG_SCSI_AHCI 342 #define CONFIG_SATA_ULI5288 343 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 344 #define CONFIG_SYS_SCSI_MAX_LUN 1 345 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 346 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 347 #endif /* SCSCI */ 348 349 #endif /* CONFIG_PCI */ 350 351 352 #if defined(CONFIG_TSEC_ENET) 353 354 #ifndef CONFIG_NET_MULTI 355 #define CONFIG_NET_MULTI 1 356 #endif 357 358 #define CONFIG_MII 1 /* MII PHY management */ 359 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 360 #define CONFIG_TSEC1 1 361 #define CONFIG_TSEC1_NAME "eTSEC1" 362 #define CONFIG_TSEC3 1 363 #define CONFIG_TSEC3_NAME "eTSEC3" 364 365 #define CONFIG_PIXIS_SGMII_CMD 366 #define CONFIG_FSL_SGMII_RISER 1 367 #define SGMII_RISER_PHY_OFFSET 0x1c 368 369 #define TSEC1_PHY_ADDR 0 370 #define TSEC3_PHY_ADDR 1 371 372 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 373 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 374 375 #define TSEC1_PHYIDX 0 376 #define TSEC3_PHYIDX 0 377 378 #define CONFIG_ETHPRIME "eTSEC1" 379 380 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 381 #endif /* CONFIG_TSEC_ENET */ 382 383 /* 384 * Environment 385 */ 386 #define CONFIG_ENV_IS_IN_FLASH 1 387 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 388 #define CONFIG_ENV_ADDR 0xfff80000 389 #else 390 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) 391 #endif 392 #define CONFIG_ENV_SIZE 0x2000 393 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 394 395 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 396 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 397 398 /* 399 * BOOTP options 400 */ 401 #define CONFIG_BOOTP_BOOTFILESIZE 402 #define CONFIG_BOOTP_BOOTPATH 403 #define CONFIG_BOOTP_GATEWAY 404 #define CONFIG_BOOTP_HOSTNAME 405 406 407 /* 408 * Command line configuration. 409 */ 410 #include <config_cmd_default.h> 411 412 #define CONFIG_CMD_PING 413 #define CONFIG_CMD_I2C 414 #define CONFIG_CMD_MII 415 #define CONFIG_CMD_ELF 416 #define CONFIG_CMD_IRQ 417 #define CONFIG_CMD_SETEXPR 418 #define CONFIG_CMD_REGINFO 419 420 #if defined(CONFIG_PCI) 421 #define CONFIG_CMD_PCI 422 #define CONFIG_CMD_NET 423 #define CONFIG_CMD_SCSI 424 #define CONFIG_CMD_EXT2 425 #endif 426 427 428 #undef CONFIG_WATCHDOG /* watchdog disabled */ 429 430 /* 431 * Miscellaneous configurable options 432 */ 433 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 434 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 435 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 436 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 437 #if defined(CONFIG_CMD_KGDB) 438 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 439 #else 440 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 441 #endif 442 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 443 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 444 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 445 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 446 447 /* 448 * For booting Linux, the board info and command line data 449 * have to be in the first 16 MB of memory, since this is 450 * the maximum mapped by the Linux kernel during initialization. 451 */ 452 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 453 454 /* 455 * Internal Definitions 456 * 457 * Boot Flags 458 */ 459 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 460 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 461 462 #if defined(CONFIG_CMD_KGDB) 463 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 464 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 465 #endif 466 467 /* 468 * Environment Configuration 469 */ 470 471 /* The mac addresses for all ethernet interface */ 472 #if defined(CONFIG_TSEC_ENET) 473 #define CONFIG_HAS_ETH0 474 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 475 #define CONFIG_HAS_ETH1 476 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 477 #endif 478 479 #define CONFIG_IPADDR 192.168.1.251 480 481 #define CONFIG_HOSTNAME 8544ds_unknown 482 #define CONFIG_ROOTPATH /nfs/mpc85xx 483 #define CONFIG_BOOTFILE 8544ds/uImage.uboot 484 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 485 486 #define CONFIG_SERVERIP 192.168.1.1 487 #define CONFIG_GATEWAYIP 192.168.1.1 488 #define CONFIG_NETMASK 255.255.0.0 489 490 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 491 492 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 493 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 494 495 #define CONFIG_BAUDRATE 115200 496 497 #define CONFIG_EXTRA_ENV_SETTINGS \ 498 "netdev=eth0\0" \ 499 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 500 "tftpflash=tftpboot $loadaddr $uboot; " \ 501 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 502 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 503 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 504 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 505 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 506 "consoledev=ttyS0\0" \ 507 "ramdiskaddr=2000000\0" \ 508 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 509 "fdtaddr=c00000\0" \ 510 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 511 "bdev=sda3\0" 512 513 #define CONFIG_NFSBOOTCOMMAND \ 514 "setenv bootargs root=/dev/nfs rw " \ 515 "nfsroot=$serverip:$rootpath " \ 516 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 517 "console=$consoledev,$baudrate $othbootargs;" \ 518 "tftp $loadaddr $bootfile;" \ 519 "tftp $fdtaddr $fdtfile;" \ 520 "bootm $loadaddr - $fdtaddr" 521 522 #define CONFIG_RAMBOOTCOMMAND \ 523 "setenv bootargs root=/dev/ram rw " \ 524 "console=$consoledev,$baudrate $othbootargs;" \ 525 "tftp $ramdiskaddr $ramdiskfile;" \ 526 "tftp $loadaddr $bootfile;" \ 527 "tftp $fdtaddr $fdtfile;" \ 528 "bootm $loadaddr $ramdiskaddr $fdtaddr" 529 530 #define CONFIG_BOOTCOMMAND \ 531 "setenv bootargs root=/dev/$bdev rw " \ 532 "console=$consoledev,$baudrate $othbootargs;" \ 533 "tftp $loadaddr $bootfile;" \ 534 "tftp $fdtaddr $fdtfile;" \ 535 "bootm $loadaddr - $fdtaddr" 536 537 #endif /* __CONFIG_H */ 538