xref: /openbmc/u-boot/include/configs/MPC8544DS.h (revision 2e0c1c7d)
1 /*
2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 /*
24  * mpc8544ds board configuration file
25  *
26  */
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29 
30 /* High Level Configuration Options */
31 #define CONFIG_BOOKE		1	/* BOOKE */
32 #define CONFIG_E500		1	/* BOOKE e500 family */
33 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
34 #define CONFIG_MPC8544		1
35 #define CONFIG_MPC8544DS	1
36 
37 #ifndef CONFIG_SYS_TEXT_BASE
38 #define CONFIG_SYS_TEXT_BASE	0xfff80000
39 #endif
40 
41 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
42 #define CONFIG_PCI1		1	/* PCI controller 1 */
43 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
44 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
45 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
46 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
47 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
48 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
49 
50 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
51 #define CONFIG_E1000		1	/* Defind e1000 pci Ethernet card*/
52 
53 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
54 #define CONFIG_ENV_OVERWRITE
55 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
56 
57 #ifndef __ASSEMBLY__
58 extern unsigned long get_board_sys_clk(unsigned long dummy);
59 #endif
60 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
61 
62 /*
63  * These can be toggled for performance analysis, otherwise use default.
64  */
65 #define CONFIG_L2_CACHE			/* toggle L2 cache */
66 #define CONFIG_BTB			/* toggle branch predition */
67 
68 /*
69  * Only possible on E500 Version 2 or newer cores.
70  */
71 #define CONFIG_ENABLE_36BIT_PHYS	1
72 
73 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
74 #define CONFIG_SYS_MEMTEST_END		0x00400000
75 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
76 
77 #define CONFIG_SYS_CCSRBAR		0xe0000000
78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
79 
80 /* DDR Setup */
81 #define CONFIG_FSL_DDR2
82 #undef CONFIG_FSL_DDR_INTERACTIVE
83 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
84 #define CONFIG_DDR_SPD
85 
86 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
87 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
88 
89 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
90 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
91 #define CONFIG_VERY_BIG_RAM
92 
93 #define CONFIG_NUM_DDR_CONTROLLERS	1
94 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
95 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
96 
97 /* I2C addresses of SPD EEPROMs */
98 #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
99 
100 /* Make sure required options are set */
101 #ifndef CONFIG_SPD_EEPROM
102 #error ("CONFIG_SPD_EEPROM is required")
103 #endif
104 
105 #undef CONFIG_CLOCKS_IN_MHZ
106 
107 /*
108  * Memory map
109  *
110  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
111  *
112  * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
113  *
114  * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
115  *
116  * 0xe000_0000	0xe00f_ffff	CCSR			1M non-cacheable
117  * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
118  *
119  * Localbus cacheable
120  *
121  * 0xf000_0000	0xf3ff_ffff	SDRAM			64M Cacheable
122  * 0xf401_0000	0xf401_3fff	L1 for stack		4K Cacheable TLB0
123  *
124  * Localbus non-cacheable
125  *
126  * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS (*)	1M non-cacheable
127  * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M non-cacheable
128  * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M non-cacheable
129  *
130  */
131 
132 /*
133  * Local Bus Definitions
134  */
135 #define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* boot TLB */
136 
137 #define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M */
138 
139 #define CONFIG_SYS_BR0_PRELIM		0xff801001
140 #define CONFIG_SYS_BR1_PRELIM		0xfe801001
141 
142 #define CONFIG_SYS_OR0_PRELIM		0xff806e65
143 #define CONFIG_SYS_OR1_PRELIM		0xff806e65
144 
145 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
146 
147 #define CONFIG_SYS_FLASH_QUIET_TEST
148 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
149 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
150 #undef	CONFIG_SYS_FLASH_CHECKSUM
151 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
152 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
153 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
154 
155 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
156 
157 #define CONFIG_FLASH_CFI_DRIVER
158 #define CONFIG_SYS_FLASH_CFI
159 #define CONFIG_SYS_FLASH_EMPTY_INFO
160 
161 #define CONFIG_SYS_LBC_NONCACHE_BASE	0xf8000000
162 
163 #define CONFIG_SYS_BR2_PRELIM		0xf8201001	/* port size 16bit */
164 #define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
165 
166 #define CONFIG_SYS_BR3_PRELIM		0xf8100801	/* port size 8bit */
167 #define CONFIG_SYS_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
168 
169 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
170 #define PIXIS_BASE	0xf8100000	/* PIXIS registers */
171 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
172 #define PIXIS_VER		0x1	/* Board version at offset 1 */
173 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
174 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
175 #define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch
176 					 * register */
177 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
178 #define PIXIS_VCTL		0x10	/* VELA Control Register */
179 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
180 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
181 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
182 #define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
183 #define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
184 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
185 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
186 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
187 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
188 #define PIXIS_VSPEED2		0x1d	/* VELA VSpeed 2 */
189 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
190 #define PIXIS_VSPEED2_TSEC1SER	0x2
191 #define PIXIS_VSPEED2_TSEC3SER	0x1
192 #define PIXIS_VCFGEN1_TSEC1SER	0x20
193 #define PIXIS_VCFGEN1_TSEC3SER	0x40
194 #define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
195 #define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
196 
197 
198 #define CONFIG_SYS_INIT_RAM_LOCK      1
199 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
200 #define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
201 
202 
203 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
204 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
205 
206 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
207 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
208 
209 /* Serial Port - controlled on board with jumper J8
210  * open - index 2
211  * shorted - index 1
212  */
213 #define CONFIG_CONS_INDEX	1
214 #define CONFIG_SYS_NS16550
215 #define CONFIG_SYS_NS16550_SERIAL
216 #define CONFIG_SYS_NS16550_REG_SIZE	1
217 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
218 
219 #define CONFIG_SYS_BAUDRATE_TABLE	\
220 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
221 
222 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
223 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
224 
225 /* Use the HUSH parser */
226 #define CONFIG_SYS_HUSH_PARSER
227 #ifdef	CONFIG_SYS_HUSH_PARSER
228 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
229 #endif
230 
231 /* pass open firmware flat tree */
232 #define CONFIG_OF_LIBFDT		1
233 #define CONFIG_OF_BOARD_SETUP		1
234 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
235 
236 /* I2C */
237 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
238 #define CONFIG_HARD_I2C		/* I2C with hardware support */
239 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
240 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
241 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
242 #define CONFIG_SYS_I2C_SLAVE		0x7F
243 #define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
244 #define CONFIG_SYS_I2C_OFFSET		0x3100
245 
246 /*
247  * General PCI
248  * Memory space is mapped 1-1, but I/O space must start from 0.
249  */
250 #define CONFIG_SYS_PCIE_VIRT		0x80000000	/* 1G PCIE TLB */
251 #define CONFIG_SYS_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
252 #define CONFIG_SYS_PCI_VIRT		0xc0000000	/* 512M PCI TLB */
253 #define CONFIG_SYS_PCI_PHYS		0xc0000000	/* 512M PCI TLB */
254 
255 #define CONFIG_SYS_PCI1_MEM_VIRT	0xc0000000
256 #define CONFIG_SYS_PCI1_MEM_BUS	0xc0000000
257 #define CONFIG_SYS_PCI1_MEM_PHYS	0xc0000000
258 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
259 #define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
260 #define CONFIG_SYS_PCI1_IO_BUS	0x00000000
261 #define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
262 #define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
263 
264 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
265 #define CONFIG_SYS_PCIE2_NAME		"Slot 1"
266 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x80000000
267 #define CONFIG_SYS_PCIE2_MEM_BUS	0x80000000
268 #define CONFIG_SYS_PCIE2_MEM_PHYS	0x80000000
269 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
270 #define CONFIG_SYS_PCIE2_IO_VIRT	0xe1010000
271 #define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
272 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe1010000
273 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
274 
275 /* controller 1, Slot 2,tgtid 2, Base address a000 */
276 #define CONFIG_SYS_PCIE1_NAME		"Slot 2"
277 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
278 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
279 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
280 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
281 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe1020000
282 #define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
283 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe1020000
284 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
285 
286 /* controller 3, direct to uli, tgtid 3, Base address b000 */
287 #define CONFIG_SYS_PCIE3_NAME		"ULI"
288 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
289 #define CONFIG_SYS_PCIE3_MEM_BUS	0xb0000000
290 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xb0000000
291 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x00100000	/* 1M */
292 #define CONFIG_SYS_PCIE3_IO_VIRT	0xb0100000	/* reuse mem LAW */
293 #define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
294 #define CONFIG_SYS_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
295 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00100000	/* 1M */
296 #define CONFIG_SYS_PCIE3_MEM_VIRT2	0xb0200000
297 #define CONFIG_SYS_PCIE3_MEM_BUS2	0xb0200000
298 #define CONFIG_SYS_PCIE3_MEM_PHYS2	0xb0200000
299 #define CONFIG_SYS_PCIE3_MEM_SIZE2	0x00200000	/* 1M */
300 
301 #if defined(CONFIG_PCI)
302 
303 /*PCIE video card used*/
304 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
305 
306 /*PCI video card used*/
307 /*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
308 
309 /* video */
310 #define CONFIG_VIDEO
311 
312 #if defined(CONFIG_VIDEO)
313 #define CONFIG_BIOSEMU
314 #define CONFIG_CFB_CONSOLE
315 #define CONFIG_VIDEO_SW_CURSOR
316 #define CONFIG_VGA_AS_SINGLE_DEVICE
317 #define CONFIG_ATI_RADEON_FB
318 #define CONFIG_VIDEO_LOGO
319 /*#define CONFIG_CONSOLE_CURSOR*/
320 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
321 #endif
322 
323 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
324 
325 #undef CONFIG_EEPRO100
326 #undef CONFIG_TULIP
327 #define CONFIG_RTL8139
328 
329 #ifndef CONFIG_PCI_PNP
330 	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
331 	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
332 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
333 #endif
334 
335 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
336 #define CONFIG_DOS_PARTITION
337 #define CONFIG_SCSI_AHCI
338 
339 #ifdef CONFIG_SCSI_AHCI
340 #define CONFIG_SATA_ULI5288
341 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
342 #define CONFIG_SYS_SCSI_MAX_LUN	1
343 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
344 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
345 #endif /* SCSCI */
346 
347 #endif	/* CONFIG_PCI */
348 
349 
350 #if defined(CONFIG_TSEC_ENET)
351 
352 #define CONFIG_MII		1	/* MII PHY management */
353 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
354 #define CONFIG_TSEC1	1
355 #define CONFIG_TSEC1_NAME	"eTSEC1"
356 #define CONFIG_TSEC3	1
357 #define CONFIG_TSEC3_NAME	"eTSEC3"
358 
359 #define CONFIG_PIXIS_SGMII_CMD
360 #define CONFIG_FSL_SGMII_RISER	1
361 #define SGMII_RISER_PHY_OFFSET	0x1c
362 
363 #define TSEC1_PHY_ADDR		0
364 #define TSEC3_PHY_ADDR		1
365 
366 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
367 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
368 
369 #define TSEC1_PHYIDX		0
370 #define TSEC3_PHYIDX		0
371 
372 #define CONFIG_ETHPRIME		"eTSEC1"
373 
374 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
375 #endif	/* CONFIG_TSEC_ENET */
376 
377 /*
378  * Environment
379  */
380 #define CONFIG_ENV_IS_IN_FLASH	1
381 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
382 #define CONFIG_ENV_ADDR		0xfff80000
383 #else
384 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x70000)
385 #endif
386 #define CONFIG_ENV_SIZE		0x2000
387 #define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) */
388 
389 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
390 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
391 
392 /*
393  * BOOTP options
394  */
395 #define CONFIG_BOOTP_BOOTFILESIZE
396 #define CONFIG_BOOTP_BOOTPATH
397 #define CONFIG_BOOTP_GATEWAY
398 #define CONFIG_BOOTP_HOSTNAME
399 
400 
401 /*
402  * Command line configuration.
403  */
404 #include <config_cmd_default.h>
405 
406 #define CONFIG_CMD_PING
407 #define CONFIG_CMD_I2C
408 #define CONFIG_CMD_MII
409 #define CONFIG_CMD_ELF
410 #define CONFIG_CMD_IRQ
411 #define CONFIG_CMD_SETEXPR
412 #define CONFIG_CMD_REGINFO
413 
414 #if defined(CONFIG_PCI)
415     #define CONFIG_CMD_PCI
416     #define CONFIG_CMD_NET
417     #define CONFIG_CMD_SCSI
418     #define CONFIG_CMD_EXT2
419 #endif
420 
421 
422 #undef CONFIG_WATCHDOG			/* watchdog disabled */
423 
424 /*
425  * Miscellaneous configurable options
426  */
427 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
428 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
429 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
430 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
431 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
432 #if defined(CONFIG_CMD_KGDB)
433 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
434 #else
435 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
436 #endif
437 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
438 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
439 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
440 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
441 
442 /*
443  * For booting Linux, the board info and command line data
444  * have to be in the first 64 MB of memory, since this is
445  * the maximum mapped by the Linux kernel during initialization.
446  */
447 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
448 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
449 
450 #if defined(CONFIG_CMD_KGDB)
451 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
452 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
453 #endif
454 
455 /*
456  * Environment Configuration
457  */
458 
459 /* The mac addresses for all ethernet interface */
460 #if defined(CONFIG_TSEC_ENET)
461 #define CONFIG_HAS_ETH0
462 #define CONFIG_ETHADDR	00:E0:0C:02:00:FD
463 #define CONFIG_HAS_ETH1
464 #define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
465 #endif
466 
467 #define CONFIG_IPADDR	192.168.1.251
468 
469 #define CONFIG_HOSTNAME	8544ds_unknown
470 #define CONFIG_ROOTPATH	"/nfs/mpc85xx"
471 #define CONFIG_BOOTFILE	"8544ds/uImage.uboot"
472 #define CONFIG_UBOOTPATH	8544ds/u-boot.bin	/* TFTP server */
473 
474 #define CONFIG_SERVERIP	192.168.1.1
475 #define CONFIG_GATEWAYIP 192.168.1.1
476 #define CONFIG_NETMASK	255.255.0.0
477 
478 #define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
479 
480 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
481 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
482 
483 #define CONFIG_BAUDRATE	115200
484 
485 #define	CONFIG_EXTRA_ENV_SETTINGS				\
486  "netdev=eth0\0"						\
487  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
488  "tftpflash=tftpboot $loadaddr $uboot; "			\
489 	"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
490 	"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
491 	"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "	\
492 	"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
493 	"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"	\
494  "consoledev=ttyS0\0"				\
495  "ramdiskaddr=2000000\0"			\
496  "ramdiskfile=8544ds/ramdisk.uboot\0"		\
497  "fdtaddr=c00000\0"				\
498  "fdtfile=8544ds/mpc8544ds.dtb\0"		\
499  "bdev=sda3\0"
500 
501 #define CONFIG_NFSBOOTCOMMAND		\
502  "setenv bootargs root=/dev/nfs rw "	\
503  "nfsroot=$serverip:$rootpath "		\
504  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
505  "console=$consoledev,$baudrate $othbootargs;"	\
506  "tftp $loadaddr $bootfile;"		\
507  "tftp $fdtaddr $fdtfile;"		\
508  "bootm $loadaddr - $fdtaddr"
509 
510 #define CONFIG_RAMBOOTCOMMAND		\
511  "setenv bootargs root=/dev/ram rw "	\
512  "console=$consoledev,$baudrate $othbootargs;"	\
513  "tftp $ramdiskaddr $ramdiskfile;"	\
514  "tftp $loadaddr $bootfile;"		\
515  "tftp $fdtaddr $fdtfile;"		\
516  "bootm $loadaddr $ramdiskaddr $fdtaddr"
517 
518 #define CONFIG_BOOTCOMMAND		\
519  "setenv bootargs root=/dev/$bdev rw "	\
520  "console=$consoledev,$baudrate $othbootargs;"	\
521  "tftp $loadaddr $bootfile;"		\
522  "tftp $fdtaddr $fdtfile;"		\
523  "bootm $loadaddr - $fdtaddr"
524 
525 #endif	/* __CONFIG_H */
526