1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8544ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8544 1 35 #define CONFIG_MPC8544DS 1 36 37 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 38 #define CONFIG_PCI1 1 /* PCI controller 1 */ 39 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 40 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 41 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 44 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 48 #define CONFIG_ENV_OVERWRITE 49 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 50 51 /* 52 * When initializing flash, if we cannot find the manufacturer ID, 53 * assume this is the AMD flash associated with the CDS board. 54 * This allows booting from a promjet. 55 */ 56 #define CONFIG_ASSUME_AMD_FLASH 57 58 #ifndef __ASSEMBLY__ 59 extern unsigned long get_board_sys_clk(unsigned long dummy); 60 #endif 61 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 62 63 /* 64 * These can be toggled for performance analysis, otherwise use default. 65 */ 66 #define CONFIG_L2_CACHE /* toggle L2 cache */ 67 #define CONFIG_BTB /* toggle branch predition */ 68 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 69 70 /* 71 * Only possible on E500 Version 2 or newer cores. 72 */ 73 #define CONFIG_ENABLE_36BIT_PHYS 1 74 75 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 76 #define CFG_MEMTEST_END 0x00400000 77 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 78 79 /* 80 * Base addresses -- Note these are effective addresses where the 81 * actual resources get mapped (not physical addresses) 82 */ 83 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 84 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 85 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 86 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 87 88 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 89 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 90 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) 91 #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) 92 93 /* DDR Setup */ 94 #define CONFIG_FSL_DDR2 95 #undef CONFIG_FSL_DDR_INTERACTIVE 96 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 97 #define CONFIG_DDR_SPD 98 99 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 100 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 101 102 #define CFG_DDR_SDRAM_BASE 0x00000000 103 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 104 #define CONFIG_VERY_BIG_RAM 105 106 #define CONFIG_NUM_DDR_CONTROLLERS 1 107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 109 110 /* I2C addresses of SPD EEPROMs */ 111 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 112 113 /* Make sure required options are set */ 114 #ifndef CONFIG_SPD_EEPROM 115 #error ("CONFIG_SPD_EEPROM is required") 116 #endif 117 118 #undef CONFIG_CLOCKS_IN_MHZ 119 120 /* 121 * Memory map 122 * 123 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 124 * 125 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 126 * 127 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 128 * 129 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 130 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 131 * 132 * Localbus cacheable 133 * 134 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 135 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 136 * 137 * Localbus non-cacheable 138 * 139 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 140 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 141 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 142 * 143 */ 144 145 /* 146 * Local Bus Definitions 147 */ 148 #define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */ 149 150 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 151 152 #define CFG_BR0_PRELIM 0xff801001 153 #define CFG_BR1_PRELIM 0xfe801001 154 155 #define CFG_OR0_PRELIM 0xff806e65 156 #define CFG_OR1_PRELIM 0xff806e65 157 158 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} 159 160 #define CFG_FLASH_QUIET_TEST 161 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 162 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 163 #undef CFG_FLASH_CHECKSUM 164 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 165 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 166 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 167 168 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 169 170 #define CONFIG_FLASH_CFI_DRIVER 171 #define CFG_FLASH_CFI 172 #define CFG_FLASH_EMPTY_INFO 173 174 #define CFG_LBC_NONCACHE_BASE 0xf8000000 175 176 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ 177 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 178 179 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ 180 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 181 182 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 183 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 184 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 185 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 186 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 187 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 188 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 189 * register */ 190 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 191 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 192 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 193 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 194 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 195 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 196 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 197 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 198 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 199 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 200 #define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 201 #define PIXIS_VSPEED2_TSEC1SER 0x2 202 #define PIXIS_VSPEED2_TSEC3SER 0x1 203 #define PIXIS_VCFGEN1_TSEC1SER 0x20 204 #define PIXIS_VCFGEN1_TSEC3SER 0x40 205 206 207 /* define to use L1 as initial stack */ 208 #define CONFIG_L1_INIT_RAM 209 #define CFG_INIT_RAM_LOCK 1 210 #define CFG_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 211 #define CFG_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 212 213 214 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 215 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 216 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 217 218 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 219 #define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 220 221 /* Serial Port - controlled on board with jumper J8 222 * open - index 2 223 * shorted - index 1 224 */ 225 #define CONFIG_CONS_INDEX 1 226 #undef CONFIG_SERIAL_SOFTWARE_FIFO 227 #define CFG_NS16550 228 #define CFG_NS16550_SERIAL 229 #define CFG_NS16550_REG_SIZE 1 230 #define CFG_NS16550_CLK get_bus_freq(0) 231 232 #define CFG_BAUDRATE_TABLE \ 233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 234 235 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 236 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 237 238 /* Use the HUSH parser */ 239 #define CFG_HUSH_PARSER 240 #ifdef CFG_HUSH_PARSER 241 #define CFG_PROMPT_HUSH_PS2 "> " 242 #endif 243 244 /* pass open firmware flat tree */ 245 #define CONFIG_OF_LIBFDT 1 246 #define CONFIG_OF_BOARD_SETUP 1 247 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 248 249 #define CFG_64BIT_STRTOUL 1 250 #define CFG_64BIT_VSPRINTF 1 251 252 /* I2C */ 253 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 254 #define CONFIG_HARD_I2C /* I2C with hardware support */ 255 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 256 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 257 #define CFG_I2C_EEPROM_ADDR 0x57 258 #define CFG_I2C_SLAVE 0x7F 259 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 260 #define CFG_I2C_OFFSET 0x3100 261 262 /* 263 * General PCI 264 * Memory space is mapped 1-1, but I/O space must start from 0. 265 */ 266 #define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 267 #define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 268 269 #define CFG_PCI1_MEM_BASE 0xc0000000 270 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 271 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 272 #define CFG_PCI1_IO_BASE 0x00000000 273 #define CFG_PCI1_IO_PHYS 0xe1000000 274 #define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */ 275 276 /* PCI view of System Memory */ 277 #define CFG_PCI_MEMORY_BUS 0x00000000 278 #define CFG_PCI_MEMORY_PHYS 0x00000000 279 #define CFG_PCI_MEMORY_SIZE 0x80000000 280 281 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 282 #define CFG_PCIE2_MEM_BASE 0x80000000 283 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE 284 #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 285 #define CFG_PCIE2_IO_BASE 0x00000000 286 #define CFG_PCIE2_IO_PHYS 0xe1010000 287 #define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */ 288 289 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 290 #define CFG_PCIE1_MEM_BASE 0xa0000000 291 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 292 #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 293 #define CFG_PCIE1_IO_BASE 0x00000000 294 #define CFG_PCIE1_IO_PHYS 0xe1020000 295 #define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */ 296 297 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 298 #define CFG_PCIE3_MEM_BASE 0xb0000000 299 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE 300 #define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 301 #define CFG_PCIE3_IO_BASE 0x00000000 302 #define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 303 #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ 304 #define CFG_PCIE3_MEM_BASE2 0xb0200000 305 #define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2 306 #define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 307 308 #if defined(CONFIG_PCI) 309 310 /*PCIE video card used*/ 311 #define VIDEO_IO_OFFSET CFG_PCIE2_IO_PHYS 312 313 /*PCI video card used*/ 314 /*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/ 315 316 /* video */ 317 #define CONFIG_VIDEO 318 319 #if defined(CONFIG_VIDEO) 320 #define CONFIG_BIOSEMU 321 #define CONFIG_CFB_CONSOLE 322 #define CONFIG_VIDEO_SW_CURSOR 323 #define CONFIG_VGA_AS_SINGLE_DEVICE 324 #define CONFIG_ATI_RADEON_FB 325 #define CONFIG_VIDEO_LOGO 326 /*#define CONFIG_CONSOLE_CURSOR*/ 327 #define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 328 #endif 329 330 #define CONFIG_NET_MULTI 331 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 332 333 #undef CONFIG_EEPRO100 334 #undef CONFIG_TULIP 335 #define CONFIG_RTL8139 336 337 #ifdef CONFIG_RTL8139 338 /* This macro is used by RTL8139 but not defined in PPC architecture */ 339 #define KSEG1ADDR(x) (x) 340 #define _IO_BASE 0x00000000 341 #endif 342 343 #ifndef CONFIG_PCI_PNP 344 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE 345 #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE 346 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 347 #endif 348 349 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 350 #define CONFIG_DOS_PARTITION 351 #define CONFIG_SCSI_AHCI 352 353 #ifdef CONFIG_SCSI_AHCI 354 #define CONFIG_SATA_ULI5288 355 #define CFG_SCSI_MAX_SCSI_ID 4 356 #define CFG_SCSI_MAX_LUN 1 357 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 358 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 359 #endif /* SCSCI */ 360 361 #endif /* CONFIG_PCI */ 362 363 364 #if defined(CONFIG_TSEC_ENET) 365 366 #ifndef CONFIG_NET_MULTI 367 #define CONFIG_NET_MULTI 1 368 #endif 369 370 #define CONFIG_MII 1 /* MII PHY management */ 371 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 372 #define CONFIG_TSEC1 1 373 #define CONFIG_TSEC1_NAME "eTSEC1" 374 #define CONFIG_TSEC3 1 375 #define CONFIG_TSEC3_NAME "eTSEC3" 376 377 #define CONFIG_FSL_SGMII_RISER 1 378 #define SGMII_RISER_PHY_OFFSET 0x1c 379 380 #define TSEC1_PHY_ADDR 0 381 #define TSEC3_PHY_ADDR 1 382 383 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 384 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 385 386 #define TSEC1_PHYIDX 0 387 #define TSEC3_PHYIDX 0 388 389 #define CONFIG_ETHPRIME "eTSEC1" 390 391 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 392 #endif /* CONFIG_TSEC_ENET */ 393 394 /* 395 * Environment 396 */ 397 #define CFG_ENV_IS_IN_FLASH 1 398 #if CFG_MONITOR_BASE > 0xfff80000 399 #define CFG_ENV_ADDR 0xfff80000 400 #else 401 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000) 402 #endif 403 #define CFG_ENV_SIZE 0x2000 404 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 405 406 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 407 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 408 409 /* 410 * BOOTP options 411 */ 412 #define CONFIG_BOOTP_BOOTFILESIZE 413 #define CONFIG_BOOTP_BOOTPATH 414 #define CONFIG_BOOTP_GATEWAY 415 #define CONFIG_BOOTP_HOSTNAME 416 417 418 /* 419 * Command line configuration. 420 */ 421 #include <config_cmd_default.h> 422 423 #define CONFIG_CMD_PING 424 #define CONFIG_CMD_I2C 425 #define CONFIG_CMD_MII 426 #define CONFIG_CMD_ELF 427 428 #if defined(CONFIG_PCI) 429 #define CONFIG_CMD_PCI 430 #define CONFIG_CMD_BEDBUG 431 #define CONFIG_CMD_NET 432 #define CONFIG_CMD_SCSI 433 #define CONFIG_CMD_EXT2 434 #endif 435 436 437 #undef CONFIG_WATCHDOG /* watchdog disabled */ 438 439 /* 440 * Miscellaneous configurable options 441 */ 442 #define CFG_LONGHELP /* undef to save memory */ 443 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 444 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 445 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 446 #if defined(CONFIG_CMD_KGDB) 447 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 448 #else 449 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 450 #endif 451 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 452 #define CFG_MAXARGS 16 /* max number of command args */ 453 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 454 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 455 456 /* 457 * For booting Linux, the board info and command line data 458 * have to be in the first 8 MB of memory, since this is 459 * the maximum mapped by the Linux kernel during initialization. 460 */ 461 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 462 463 /* 464 * Internal Definitions 465 * 466 * Boot Flags 467 */ 468 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 469 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 470 471 #if defined(CONFIG_CMD_KGDB) 472 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 473 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 474 #endif 475 476 /* 477 * Environment Configuration 478 */ 479 480 /* The mac addresses for all ethernet interface */ 481 #if defined(CONFIG_TSEC_ENET) 482 #define CONFIG_HAS_ETH0 483 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 484 #define CONFIG_HAS_ETH1 485 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 486 #endif 487 488 #define CONFIG_IPADDR 192.168.1.251 489 490 #define CONFIG_HOSTNAME 8544ds_unknown 491 #define CONFIG_ROOTPATH /nfs/mpc85xx 492 #define CONFIG_BOOTFILE 8544ds/uImage.uboot 493 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 494 495 #define CONFIG_SERVERIP 192.168.1.1 496 #define CONFIG_GATEWAYIP 192.168.1.1 497 #define CONFIG_NETMASK 255.255.0.0 498 499 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 500 501 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 502 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 503 504 #define CONFIG_BAUDRATE 115200 505 506 #define CONFIG_EXTRA_ENV_SETTINGS \ 507 "netdev=eth0\0" \ 508 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 509 "tftpflash=tftpboot $loadaddr $uboot; " \ 510 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 511 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 512 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 513 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 514 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 515 "consoledev=ttyS0\0" \ 516 "ramdiskaddr=2000000\0" \ 517 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 518 "fdtaddr=c00000\0" \ 519 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 520 "bdev=sda3\0" 521 522 #define CONFIG_NFSBOOTCOMMAND \ 523 "setenv bootargs root=/dev/nfs rw " \ 524 "nfsroot=$serverip:$rootpath " \ 525 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 526 "console=$consoledev,$baudrate $othbootargs;" \ 527 "tftp $loadaddr $bootfile;" \ 528 "tftp $fdtaddr $fdtfile;" \ 529 "bootm $loadaddr - $fdtaddr" 530 531 #define CONFIG_RAMBOOTCOMMAND \ 532 "setenv bootargs root=/dev/ram rw " \ 533 "console=$consoledev,$baudrate $othbootargs;" \ 534 "tftp $ramdiskaddr $ramdiskfile;" \ 535 "tftp $loadaddr $bootfile;" \ 536 "tftp $fdtaddr $fdtfile;" \ 537 "bootm $loadaddr $ramdiskaddr $fdtaddr" 538 539 #define CONFIG_BOOTCOMMAND \ 540 "setenv bootargs root=/dev/$bdev rw " \ 541 "console=$consoledev,$baudrate $othbootargs;" \ 542 "tftp $loadaddr $bootfile;" \ 543 "tftp $fdtaddr $fdtfile;" \ 544 "bootm $loadaddr - $fdtaddr" 545 546 #endif /* __CONFIG_H */ 547