1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8541cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 36 #define CONFIG_CPM2 1 /* has CPM2 */ 37 #define CONFIG_MPC8541 1 /* MPC8541 specific */ 38 #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ 39 40 #define CONFIG_PCI 41 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 42 #define CONFIG_ENV_OVERWRITE 43 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 44 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 45 #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 46 47 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 48 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 49 50 51 /* 52 * When initializing flash, if we cannot find the manufacturer ID, 53 * assume this is the AMD flash associated with the CDS board. 54 * This allows booting from a promjet. 55 */ 56 #define CONFIG_ASSUME_AMD_FLASH 57 58 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 59 60 #ifndef __ASSEMBLY__ 61 extern unsigned long get_clock_freq(void); 62 #endif 63 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 64 65 /* 66 * These can be toggled for performance analysis, otherwise use default. 67 */ 68 #define CONFIG_L2_CACHE /* toggle L2 cache */ 69 #define CONFIG_BTB /* toggle branch predition */ 70 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 71 72 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 73 74 #undef CFG_DRAM_TEST /* memory test, takes time */ 75 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 76 #define CFG_MEMTEST_END 0x00400000 77 78 /* 79 * Base addresses -- Note these are effective addresses where the 80 * actual resources get mapped (not physical addresses) 81 */ 82 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 83 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 84 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 85 86 /* 87 * DDR Setup 88 */ 89 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 90 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 91 92 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 93 94 /* 95 * Make sure required options are set 96 */ 97 #ifndef CONFIG_SPD_EEPROM 98 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 99 #endif 100 101 #undef CONFIG_CLOCKS_IN_MHZ 102 103 104 /* 105 * Local Bus Definitions 106 */ 107 108 /* 109 * FLASH on the Local Bus 110 * Two banks, 8M each, using the CFI driver. 111 * Boot from BR0/OR0 bank at 0xff00_0000 112 * Alternate BR1/OR1 bank at 0xff80_0000 113 * 114 * BR0, BR1: 115 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 116 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 117 * Port Size = 16 bits = BRx[19:20] = 10 118 * Use GPCM = BRx[24:26] = 000 119 * Valid = BRx[31] = 1 120 * 121 * 0 4 8 12 16 20 24 28 122 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 123 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 124 * 125 * OR0, OR1: 126 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 127 * Reserved ORx[17:18] = 11, confusion here? 128 * CSNT = ORx[20] = 1 129 * ACS = half cycle delay = ORx[21:22] = 11 130 * SCY = 6 = ORx[24:27] = 0110 131 * TRLX = use relaxed timing = ORx[29] = 1 132 * EAD = use external address latch delay = OR[31] = 1 133 * 134 * 0 4 8 12 16 20 24 28 135 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 136 */ 137 138 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 139 140 #define CFG_BR0_PRELIM 0xff801001 141 #define CFG_BR1_PRELIM 0xff001001 142 143 #define CFG_OR0_PRELIM 0xff806e65 144 #define CFG_OR1_PRELIM 0xff806e65 145 146 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} 147 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 148 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 149 #undef CFG_FLASH_CHECKSUM 150 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 151 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 152 153 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 154 155 #define CFG_FLASH_CFI_DRIVER 156 #define CFG_FLASH_CFI 157 #define CFG_FLASH_EMPTY_INFO 158 159 160 /* 161 * SDRAM on the Local Bus 162 */ 163 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 164 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 165 166 /* 167 * Base Register 2 and Option Register 2 configure SDRAM. 168 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 169 * 170 * For BR2, need: 171 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 172 * port-size = 32-bits = BR2[19:20] = 11 173 * no parity checking = BR2[21:22] = 00 174 * SDRAM for MSEL = BR2[24:26] = 011 175 * Valid = BR[31] = 1 176 * 177 * 0 4 8 12 16 20 24 28 178 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 179 * 180 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 181 * FIXME: the top 17 bits of BR2. 182 */ 183 184 #define CFG_BR2_PRELIM 0xf0001861 185 186 /* 187 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 188 * 189 * For OR2, need: 190 * 64MB mask for AM, OR2[0:7] = 1111 1100 191 * XAM, OR2[17:18] = 11 192 * 9 columns OR2[19-21] = 010 193 * 13 rows OR2[23-25] = 100 194 * EAD set for extra time OR[31] = 1 195 * 196 * 0 4 8 12 16 20 24 28 197 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 198 */ 199 200 #define CFG_OR2_PRELIM 0xfc006901 201 202 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 203 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 204 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 205 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 206 207 /* 208 * LSDMR masks 209 */ 210 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 211 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 212 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 213 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 214 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 215 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 216 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 217 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 218 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 219 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 220 221 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 222 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 223 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 224 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 225 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 229 230 /* 231 * Common settings for all Local Bus SDRAM commands. 232 * At run time, either BSMA1516 (for CPU 1.1) 233 * or BSMA1617 (for CPU 1.0) (old) 234 * is OR'ed in too. 235 */ 236 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 237 | CFG_LBC_LSDMR_PRETOACT7 \ 238 | CFG_LBC_LSDMR_ACTTORW7 \ 239 | CFG_LBC_LSDMR_BL8 \ 240 | CFG_LBC_LSDMR_WRC4 \ 241 | CFG_LBC_LSDMR_CL3 \ 242 | CFG_LBC_LSDMR_RFEN \ 243 ) 244 245 /* 246 * The CADMUS registers are connected to CS3 on CDS. 247 * The new memory map places CADMUS at 0xf8000000. 248 * 249 * For BR3, need: 250 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 251 * port-size = 8-bits = BR[19:20] = 01 252 * no parity checking = BR[21:22] = 00 253 * GPMC for MSEL = BR[24:26] = 000 254 * Valid = BR[31] = 1 255 * 256 * 0 4 8 12 16 20 24 28 257 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 258 * 259 * For OR3, need: 260 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 261 * disable buffer ctrl OR[19] = 0 262 * CSNT OR[20] = 1 263 * ACS OR[21:22] = 11 264 * XACS OR[23] = 1 265 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 266 * SETA OR[28] = 0 267 * TRLX OR[29] = 1 268 * EHTR OR[30] = 1 269 * EAD extra time OR[31] = 1 270 * 271 * 0 4 8 12 16 20 24 28 272 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 273 */ 274 275 #define CADMUS_BASE_ADDR 0xf8000000 276 #define CFG_BR3_PRELIM 0xf8000801 277 #define CFG_OR3_PRELIM 0xfff00ff7 278 279 #define CONFIG_L1_INIT_RAM 280 #define CFG_INIT_RAM_LOCK 1 281 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 282 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 283 284 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 285 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 286 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 287 288 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 289 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 290 291 /* Serial Port */ 292 #define CONFIG_CONS_INDEX 2 293 #undef CONFIG_SERIAL_SOFTWARE_FIFO 294 #define CFG_NS16550 295 #define CFG_NS16550_SERIAL 296 #define CFG_NS16550_REG_SIZE 1 297 #define CFG_NS16550_CLK get_bus_freq(0) 298 299 #define CFG_BAUDRATE_TABLE \ 300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 301 302 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 303 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 304 305 /* Use the HUSH parser */ 306 #define CFG_HUSH_PARSER 307 #ifdef CFG_HUSH_PARSER 308 #define CFG_PROMPT_HUSH_PS2 "> " 309 #endif 310 311 /* pass open firmware flat tree */ 312 #define CONFIG_OF_FLAT_TREE 1 313 #define CONFIG_OF_BOARD_SETUP 1 314 315 /* maximum size of the flat tree (8K) */ 316 #define OF_FLAT_TREE_MAX_SIZE 8192 317 318 #define OF_CPU "PowerPC,8541@0" 319 #define OF_SOC "soc8541@e0000000" 320 #define OF_TBCLK (bd->bi_busfreq / 8) 321 #define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" 322 323 /* I2C */ 324 #define CONFIG_HARD_I2C /* I2C with hardware support */ 325 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 326 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 327 #define CFG_I2C_EEPROM_ADDR 0x57 328 #define CFG_I2C_SLAVE 0x7F 329 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 330 331 /* 332 * General PCI 333 * Addresses are mapped 1-1. 334 */ 335 #define CFG_PCI1_MEM_BASE 0x80000000 336 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 337 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 338 #define CFG_PCI1_IO_BASE 0x00000000 339 #define CFG_PCI1_IO_PHYS 0xe2000000 340 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ 341 342 #define CFG_PCI2_MEM_BASE 0xa0000000 343 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 344 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 345 #define CFG_PCI2_IO_BASE 0x00000000 346 #define CFG_PCI2_IO_PHYS 0xe2100000 347 #define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ 348 349 350 #if defined(CONFIG_PCI) 351 352 #define CONFIG_MPC85XX_PCI2 353 #define CONFIG_NET_MULTI 354 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 355 356 #undef CONFIG_EEPRO100 357 #undef CONFIG_TULIP 358 359 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 360 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 361 362 #endif /* CONFIG_PCI */ 363 364 365 #if defined(CONFIG_TSEC_ENET) 366 367 #ifndef CONFIG_NET_MULTI 368 #define CONFIG_NET_MULTI 1 369 #endif 370 371 #define CONFIG_MII 1 /* MII PHY management */ 372 #define CONFIG_MPC85XX_TSEC1 1 373 #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" 374 #define CONFIG_MPC85XX_TSEC2 1 375 #define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" 376 #undef CONFIG_MPC85XX_FEC 377 #define TSEC1_PHY_ADDR 0 378 #define TSEC2_PHY_ADDR 1 379 #define FEC_PHY_ADDR 3 380 #define TSEC1_PHYIDX 0 381 #define TSEC2_PHYIDX 0 382 #define FEC_PHYIDX 0 383 384 /* Options are: TSEC[0-1] */ 385 #define CONFIG_ETHPRIME "TSEC0" 386 387 #endif /* CONFIG_TSEC_ENET */ 388 389 /* 390 * Environment 391 */ 392 #define CFG_ENV_IS_IN_FLASH 1 393 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 394 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 395 #define CFG_ENV_SIZE 0x2000 396 397 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 398 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 399 400 #if defined(CONFIG_PCI) 401 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 402 | CFG_CMD_PCI \ 403 | CFG_CMD_PING \ 404 | CFG_CMD_I2C \ 405 | CFG_CMD_MII) 406 #else 407 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 408 | CFG_CMD_PING \ 409 | CFG_CMD_I2C \ 410 | CFG_CMD_MII) 411 #endif 412 #include <cmd_confdefs.h> 413 414 #undef CONFIG_WATCHDOG /* watchdog disabled */ 415 416 /* 417 * Miscellaneous configurable options 418 */ 419 #define CFG_LONGHELP /* undef to save memory */ 420 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 421 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 422 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 423 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 424 #else 425 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 426 #endif 427 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 428 #define CFG_MAXARGS 16 /* max number of command args */ 429 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 430 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 431 432 /* 433 * For booting Linux, the board info and command line data 434 * have to be in the first 8 MB of memory, since this is 435 * the maximum mapped by the Linux kernel during initialization. 436 */ 437 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 438 439 /* Cache Configuration */ 440 #define CFG_DCACHE_SIZE 32768 441 #define CFG_CACHELINE_SIZE 32 442 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 443 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 444 #endif 445 446 /* 447 * Internal Definitions 448 * 449 * Boot Flags 450 */ 451 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 452 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 453 454 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 455 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 456 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 457 #endif 458 459 /* 460 * Environment Configuration 461 */ 462 463 /* The mac addresses for all ethernet interface */ 464 #if defined(CONFIG_TSEC_ENET) 465 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 466 #define CONFIG_HAS_ETH1 467 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 468 #define CONFIG_HAS_ETH2 469 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 470 #endif 471 472 #define CONFIG_IPADDR 192.168.1.253 473 474 #define CONFIG_HOSTNAME unknown 475 #define CONFIG_ROOTPATH /nfsroot 476 #define CONFIG_BOOTFILE your.uImage 477 478 #define CONFIG_SERVERIP 192.168.1.1 479 #define CONFIG_GATEWAYIP 192.168.1.1 480 #define CONFIG_NETMASK 255.255.255.0 481 482 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 483 484 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 485 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 486 487 #define CONFIG_BAUDRATE 115200 488 489 #define CONFIG_EXTRA_ENV_SETTINGS \ 490 "netdev=eth0\0" \ 491 "consoledev=ttyS1\0" \ 492 "ramdiskaddr=400000\0" \ 493 "ramdiskfile=your.ramdisk.u-boot\0" 494 495 #define CONFIG_NFSBOOTCOMMAND \ 496 "setenv bootargs root=/dev/nfs rw " \ 497 "nfsroot=$serverip:$rootpath " \ 498 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 499 "console=$consoledev,$baudrate $othbootargs;" \ 500 "tftp $loadaddr $bootfile;" \ 501 "bootm $loadaddr" 502 503 #define CONFIG_RAMBOOTCOMMAND \ 504 "setenv bootargs root=/dev/ram rw " \ 505 "console=$consoledev,$baudrate $othbootargs;" \ 506 "tftp $ramdiskaddr $ramdiskfile;" \ 507 "tftp $loadaddr $bootfile;" \ 508 "bootm $loadaddr $ramdiskaddr" 509 510 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 511 512 #endif /* __CONFIG_H */ 513