1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8541cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_CPM2 1 /* has CPM2 */ 18 19 #define CONFIG_SYS_TEXT_BASE 0xfff80000 20 21 #define CONFIG_PCI_INDIRECT_BRIDGE 22 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 23 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 24 #define CONFIG_ENV_OVERWRITE 25 26 #define CONFIG_FSL_VIA 27 28 #ifndef __ASSEMBLY__ 29 extern unsigned long get_clock_freq(void); 30 #endif 31 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 32 33 /* 34 * These can be toggled for performance analysis, otherwise use default. 35 */ 36 #define CONFIG_L2_CACHE /* toggle L2 cache */ 37 #define CONFIG_BTB /* toggle branch predition */ 38 39 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 40 #define CONFIG_SYS_MEMTEST_END 0x00400000 41 42 #define CONFIG_SYS_CCSRBAR 0xe0000000 43 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 44 45 /* DDR Setup */ 46 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 47 #define CONFIG_DDR_SPD 48 #undef CONFIG_FSL_DDR_INTERACTIVE 49 50 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 51 52 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 53 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 54 55 #define CONFIG_NUM_DDR_CONTROLLERS 1 56 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 57 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 58 59 /* I2C addresses of SPD EEPROMs */ 60 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 61 62 /* 63 * Make sure required options are set 64 */ 65 #ifndef CONFIG_SPD_EEPROM 66 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 67 #endif 68 69 #undef CONFIG_CLOCKS_IN_MHZ 70 71 /* 72 * Local Bus Definitions 73 */ 74 75 /* 76 * FLASH on the Local Bus 77 * Two banks, 8M each, using the CFI driver. 78 * Boot from BR0/OR0 bank at 0xff00_0000 79 * Alternate BR1/OR1 bank at 0xff80_0000 80 * 81 * BR0, BR1: 82 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 83 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 84 * Port Size = 16 bits = BRx[19:20] = 10 85 * Use GPCM = BRx[24:26] = 000 86 * Valid = BRx[31] = 1 87 * 88 * 0 4 8 12 16 20 24 28 89 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 90 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 91 * 92 * OR0, OR1: 93 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 94 * Reserved ORx[17:18] = 11, confusion here? 95 * CSNT = ORx[20] = 1 96 * ACS = half cycle delay = ORx[21:22] = 11 97 * SCY = 6 = ORx[24:27] = 0110 98 * TRLX = use relaxed timing = ORx[29] = 1 99 * EAD = use external address latch delay = OR[31] = 1 100 * 101 * 0 4 8 12 16 20 24 28 102 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 103 */ 104 105 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 106 107 #define CONFIG_SYS_BR0_PRELIM 0xff801001 108 #define CONFIG_SYS_BR1_PRELIM 0xff001001 109 110 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 111 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 112 113 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 114 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 115 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 116 #undef CONFIG_SYS_FLASH_CHECKSUM 117 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 118 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 119 120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 121 122 #define CONFIG_FLASH_CFI_DRIVER 123 #define CONFIG_SYS_FLASH_CFI 124 #define CONFIG_SYS_FLASH_EMPTY_INFO 125 126 /* 127 * SDRAM on the Local Bus 128 */ 129 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 130 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 131 132 /* 133 * Base Register 2 and Option Register 2 configure SDRAM. 134 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 135 * 136 * For BR2, need: 137 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 138 * port-size = 32-bits = BR2[19:20] = 11 139 * no parity checking = BR2[21:22] = 00 140 * SDRAM for MSEL = BR2[24:26] = 011 141 * Valid = BR[31] = 1 142 * 143 * 0 4 8 12 16 20 24 28 144 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 145 * 146 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 147 * FIXME: the top 17 bits of BR2. 148 */ 149 150 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 151 152 /* 153 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 154 * 155 * For OR2, need: 156 * 64MB mask for AM, OR2[0:7] = 1111 1100 157 * XAM, OR2[17:18] = 11 158 * 9 columns OR2[19-21] = 010 159 * 13 rows OR2[23-25] = 100 160 * EAD set for extra time OR[31] = 1 161 * 162 * 0 4 8 12 16 20 24 28 163 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 164 */ 165 166 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 167 168 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 169 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 170 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 171 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 172 173 /* 174 * Common settings for all Local Bus SDRAM commands. 175 * At run time, either BSMA1516 (for CPU 1.1) 176 * or BSMA1617 (for CPU 1.0) (old) 177 * is OR'ed in too. 178 */ 179 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 180 | LSDMR_PRETOACT7 \ 181 | LSDMR_ACTTORW7 \ 182 | LSDMR_BL8 \ 183 | LSDMR_WRC4 \ 184 | LSDMR_CL3 \ 185 | LSDMR_RFEN \ 186 ) 187 188 /* 189 * The CADMUS registers are connected to CS3 on CDS. 190 * The new memory map places CADMUS at 0xf8000000. 191 * 192 * For BR3, need: 193 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 194 * port-size = 8-bits = BR[19:20] = 01 195 * no parity checking = BR[21:22] = 00 196 * GPMC for MSEL = BR[24:26] = 000 197 * Valid = BR[31] = 1 198 * 199 * 0 4 8 12 16 20 24 28 200 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 201 * 202 * For OR3, need: 203 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 204 * disable buffer ctrl OR[19] = 0 205 * CSNT OR[20] = 1 206 * ACS OR[21:22] = 11 207 * XACS OR[23] = 1 208 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 209 * SETA OR[28] = 0 210 * TRLX OR[29] = 1 211 * EHTR OR[30] = 1 212 * EAD extra time OR[31] = 1 213 * 214 * 0 4 8 12 16 20 24 28 215 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 216 */ 217 218 #define CONFIG_FSL_CADMUS 219 220 #define CADMUS_BASE_ADDR 0xf8000000 221 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 222 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 223 224 #define CONFIG_SYS_INIT_RAM_LOCK 1 225 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 226 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 227 228 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 229 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 230 231 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 232 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 233 234 /* Serial Port */ 235 #define CONFIG_CONS_INDEX 2 236 #define CONFIG_SYS_NS16550_SERIAL 237 #define CONFIG_SYS_NS16550_REG_SIZE 1 238 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 239 240 #define CONFIG_SYS_BAUDRATE_TABLE \ 241 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 242 243 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 244 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 245 246 /* 247 * I2C 248 */ 249 #define CONFIG_SYS_I2C 250 #define CONFIG_SYS_I2C_FSL 251 #define CONFIG_SYS_FSL_I2C_SPEED 400000 252 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 253 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 254 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 255 256 /* EEPROM */ 257 #define CONFIG_ID_EEPROM 258 #define CONFIG_SYS_I2C_EEPROM_CCID 259 #define CONFIG_SYS_ID_EEPROM 260 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 261 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 262 263 /* 264 * General PCI 265 * Memory space is mapped 1-1, but I/O space must start from 0. 266 */ 267 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 268 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 269 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 270 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 271 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 272 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 273 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 274 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 275 276 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 277 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 278 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 279 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 280 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 281 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 282 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 283 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ 284 285 #ifdef CONFIG_LEGACY 286 #define BRIDGE_ID 17 287 #define VIA_ID 2 288 #else 289 #define BRIDGE_ID 28 290 #define VIA_ID 4 291 #endif 292 293 #if defined(CONFIG_PCI) 294 295 #define CONFIG_MPC85XX_PCI2 296 297 #undef CONFIG_EEPRO100 298 #undef CONFIG_TULIP 299 300 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 301 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 302 303 #endif /* CONFIG_PCI */ 304 305 #if defined(CONFIG_TSEC_ENET) 306 307 #define CONFIG_MII 1 /* MII PHY management */ 308 #define CONFIG_TSEC1 1 309 #define CONFIG_TSEC1_NAME "TSEC0" 310 #define CONFIG_TSEC2 1 311 #define CONFIG_TSEC2_NAME "TSEC1" 312 #define TSEC1_PHY_ADDR 0 313 #define TSEC2_PHY_ADDR 1 314 #define TSEC1_PHYIDX 0 315 #define TSEC2_PHYIDX 0 316 #define TSEC1_FLAGS TSEC_GIGABIT 317 #define TSEC2_FLAGS TSEC_GIGABIT 318 319 /* Options are: TSEC[0-1] */ 320 #define CONFIG_ETHPRIME "TSEC0" 321 322 #endif /* CONFIG_TSEC_ENET */ 323 324 /* 325 * Environment 326 */ 327 #define CONFIG_ENV_IS_IN_FLASH 1 328 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 329 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 330 #define CONFIG_ENV_SIZE 0x2000 331 332 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 333 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 334 335 /* 336 * BOOTP options 337 */ 338 #define CONFIG_BOOTP_BOOTFILESIZE 339 #define CONFIG_BOOTP_BOOTPATH 340 #define CONFIG_BOOTP_GATEWAY 341 #define CONFIG_BOOTP_HOSTNAME 342 343 /* 344 * Command line configuration. 345 */ 346 #define CONFIG_CMD_IRQ 347 #define CONFIG_CMD_REGINFO 348 349 #if defined(CONFIG_PCI) 350 #define CONFIG_CMD_PCI 351 #endif 352 353 #undef CONFIG_WATCHDOG /* watchdog disabled */ 354 355 /* 356 * Miscellaneous configurable options 357 */ 358 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 359 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 360 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 361 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 362 #if defined(CONFIG_CMD_KGDB) 363 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 364 #else 365 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 366 #endif 367 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 368 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 369 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 370 371 /* 372 * For booting Linux, the board info and command line data 373 * have to be in the first 64 MB of memory, since this is 374 * the maximum mapped by the Linux kernel during initialization. 375 */ 376 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 377 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 378 379 #if defined(CONFIG_CMD_KGDB) 380 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 381 #endif 382 383 /* 384 * Environment Configuration 385 */ 386 387 /* The mac addresses for all ethernet interface */ 388 #if defined(CONFIG_TSEC_ENET) 389 #define CONFIG_HAS_ETH0 390 #define CONFIG_HAS_ETH1 391 #define CONFIG_HAS_ETH2 392 #endif 393 394 #define CONFIG_IPADDR 192.168.1.253 395 396 #define CONFIG_HOSTNAME unknown 397 #define CONFIG_ROOTPATH "/nfsroot" 398 #define CONFIG_BOOTFILE "your.uImage" 399 400 #define CONFIG_SERVERIP 192.168.1.1 401 #define CONFIG_GATEWAYIP 192.168.1.1 402 #define CONFIG_NETMASK 255.255.255.0 403 404 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 405 406 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 407 408 #define CONFIG_BAUDRATE 115200 409 410 #define CONFIG_EXTRA_ENV_SETTINGS \ 411 "netdev=eth0\0" \ 412 "consoledev=ttyS1\0" \ 413 "ramdiskaddr=600000\0" \ 414 "ramdiskfile=your.ramdisk.u-boot\0" \ 415 "fdtaddr=400000\0" \ 416 "fdtfile=your.fdt.dtb\0" 417 418 #define CONFIG_NFSBOOTCOMMAND \ 419 "setenv bootargs root=/dev/nfs rw " \ 420 "nfsroot=$serverip:$rootpath " \ 421 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 422 "console=$consoledev,$baudrate $othbootargs;" \ 423 "tftp $loadaddr $bootfile;" \ 424 "tftp $fdtaddr $fdtfile;" \ 425 "bootm $loadaddr - $fdtaddr" 426 427 #define CONFIG_RAMBOOTCOMMAND \ 428 "setenv bootargs root=/dev/ram rw " \ 429 "console=$consoledev,$baudrate $othbootargs;" \ 430 "tftp $ramdiskaddr $ramdiskfile;" \ 431 "tftp $loadaddr $bootfile;" \ 432 "bootm $loadaddr $ramdiskaddr" 433 434 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 435 436 #endif /* __CONFIG_H */ 437