1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8541cds board configuration file 8 * 9 * Please refer to doc/README.mpc85xxcds for more info. 10 * 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* High Level Configuration Options */ 16 #define CONFIG_CPM2 1 /* has CPM2 */ 17 18 #define CONFIG_PCI_INDIRECT_BRIDGE 19 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 20 #define CONFIG_ENV_OVERWRITE 21 22 #define CONFIG_FSL_VIA 23 24 #ifndef __ASSEMBLY__ 25 extern unsigned long get_clock_freq(void); 26 #endif 27 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 28 29 /* 30 * These can be toggled for performance analysis, otherwise use default. 31 */ 32 #define CONFIG_L2_CACHE /* toggle L2 cache */ 33 #define CONFIG_BTB /* toggle branch predition */ 34 35 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 36 #define CONFIG_SYS_MEMTEST_END 0x00400000 37 38 #define CONFIG_SYS_CCSRBAR 0xe0000000 39 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 40 41 /* DDR Setup */ 42 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 43 #define CONFIG_DDR_SPD 44 #undef CONFIG_FSL_DDR_INTERACTIVE 45 46 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 47 48 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 50 51 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 52 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 53 54 /* I2C addresses of SPD EEPROMs */ 55 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 56 57 /* 58 * Make sure required options are set 59 */ 60 #ifndef CONFIG_SPD_EEPROM 61 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 62 #endif 63 64 #undef CONFIG_CLOCKS_IN_MHZ 65 66 /* 67 * Local Bus Definitions 68 */ 69 70 /* 71 * FLASH on the Local Bus 72 * Two banks, 8M each, using the CFI driver. 73 * Boot from BR0/OR0 bank at 0xff00_0000 74 * Alternate BR1/OR1 bank at 0xff80_0000 75 * 76 * BR0, BR1: 77 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 78 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 79 * Port Size = 16 bits = BRx[19:20] = 10 80 * Use GPCM = BRx[24:26] = 000 81 * Valid = BRx[31] = 1 82 * 83 * 0 4 8 12 16 20 24 28 84 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 85 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 86 * 87 * OR0, OR1: 88 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 89 * Reserved ORx[17:18] = 11, confusion here? 90 * CSNT = ORx[20] = 1 91 * ACS = half cycle delay = ORx[21:22] = 11 92 * SCY = 6 = ORx[24:27] = 0110 93 * TRLX = use relaxed timing = ORx[29] = 1 94 * EAD = use external address latch delay = OR[31] = 1 95 * 96 * 0 4 8 12 16 20 24 28 97 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 98 */ 99 100 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 101 102 #define CONFIG_SYS_BR0_PRELIM 0xff801001 103 #define CONFIG_SYS_BR1_PRELIM 0xff001001 104 105 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 106 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 107 108 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 109 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 110 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 111 #undef CONFIG_SYS_FLASH_CHECKSUM 112 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 114 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 116 117 #define CONFIG_FLASH_CFI_DRIVER 118 #define CONFIG_SYS_FLASH_CFI 119 #define CONFIG_SYS_FLASH_EMPTY_INFO 120 121 /* 122 * SDRAM on the Local Bus 123 */ 124 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 125 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 126 127 /* 128 * Base Register 2 and Option Register 2 configure SDRAM. 129 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 130 * 131 * For BR2, need: 132 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 133 * port-size = 32-bits = BR2[19:20] = 11 134 * no parity checking = BR2[21:22] = 00 135 * SDRAM for MSEL = BR2[24:26] = 011 136 * Valid = BR[31] = 1 137 * 138 * 0 4 8 12 16 20 24 28 139 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 140 * 141 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 142 * FIXME: the top 17 bits of BR2. 143 */ 144 145 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 146 147 /* 148 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 149 * 150 * For OR2, need: 151 * 64MB mask for AM, OR2[0:7] = 1111 1100 152 * XAM, OR2[17:18] = 11 153 * 9 columns OR2[19-21] = 010 154 * 13 rows OR2[23-25] = 100 155 * EAD set for extra time OR[31] = 1 156 * 157 * 0 4 8 12 16 20 24 28 158 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 159 */ 160 161 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 162 163 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 164 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 165 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 166 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 167 168 /* 169 * Common settings for all Local Bus SDRAM commands. 170 * At run time, either BSMA1516 (for CPU 1.1) 171 * or BSMA1617 (for CPU 1.0) (old) 172 * is OR'ed in too. 173 */ 174 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 175 | LSDMR_PRETOACT7 \ 176 | LSDMR_ACTTORW7 \ 177 | LSDMR_BL8 \ 178 | LSDMR_WRC4 \ 179 | LSDMR_CL3 \ 180 | LSDMR_RFEN \ 181 ) 182 183 /* 184 * The CADMUS registers are connected to CS3 on CDS. 185 * The new memory map places CADMUS at 0xf8000000. 186 * 187 * For BR3, need: 188 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 189 * port-size = 8-bits = BR[19:20] = 01 190 * no parity checking = BR[21:22] = 00 191 * GPMC for MSEL = BR[24:26] = 000 192 * Valid = BR[31] = 1 193 * 194 * 0 4 8 12 16 20 24 28 195 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 196 * 197 * For OR3, need: 198 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 199 * disable buffer ctrl OR[19] = 0 200 * CSNT OR[20] = 1 201 * ACS OR[21:22] = 11 202 * XACS OR[23] = 1 203 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 204 * SETA OR[28] = 0 205 * TRLX OR[29] = 1 206 * EHTR OR[30] = 1 207 * EAD extra time OR[31] = 1 208 * 209 * 0 4 8 12 16 20 24 28 210 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 211 */ 212 213 #define CONFIG_FSL_CADMUS 214 215 #define CADMUS_BASE_ADDR 0xf8000000 216 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 217 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 218 219 #define CONFIG_SYS_INIT_RAM_LOCK 1 220 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 221 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 222 223 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 224 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 225 226 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 227 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 228 229 /* Serial Port */ 230 #define CONFIG_SYS_NS16550_SERIAL 231 #define CONFIG_SYS_NS16550_REG_SIZE 1 232 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 233 234 #define CONFIG_SYS_BAUDRATE_TABLE \ 235 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 236 237 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 238 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 239 240 /* 241 * I2C 242 */ 243 #define CONFIG_SYS_I2C 244 #define CONFIG_SYS_I2C_FSL 245 #define CONFIG_SYS_FSL_I2C_SPEED 400000 246 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 247 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 248 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 249 250 /* EEPROM */ 251 #define CONFIG_ID_EEPROM 252 #define CONFIG_SYS_I2C_EEPROM_CCID 253 #define CONFIG_SYS_ID_EEPROM 254 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 255 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 256 257 /* 258 * General PCI 259 * Memory space is mapped 1-1, but I/O space must start from 0. 260 */ 261 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 262 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 263 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 264 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 265 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 266 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 267 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 268 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 269 270 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 271 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 272 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 273 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 274 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 275 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 276 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 277 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ 278 279 #ifdef CONFIG_LEGACY 280 #define BRIDGE_ID 17 281 #define VIA_ID 2 282 #else 283 #define BRIDGE_ID 28 284 #define VIA_ID 4 285 #endif 286 287 #if defined(CONFIG_PCI) 288 289 #define CONFIG_MPC85XX_PCI2 290 291 #undef CONFIG_EEPRO100 292 #undef CONFIG_TULIP 293 294 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 295 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 296 297 #endif /* CONFIG_PCI */ 298 299 #if defined(CONFIG_TSEC_ENET) 300 301 #define CONFIG_MII 1 /* MII PHY management */ 302 #define CONFIG_TSEC1 1 303 #define CONFIG_TSEC1_NAME "TSEC0" 304 #define CONFIG_TSEC2 1 305 #define CONFIG_TSEC2_NAME "TSEC1" 306 #define TSEC1_PHY_ADDR 0 307 #define TSEC2_PHY_ADDR 1 308 #define TSEC1_PHYIDX 0 309 #define TSEC2_PHYIDX 0 310 #define TSEC1_FLAGS TSEC_GIGABIT 311 #define TSEC2_FLAGS TSEC_GIGABIT 312 313 /* Options are: TSEC[0-1] */ 314 #define CONFIG_ETHPRIME "TSEC0" 315 316 #endif /* CONFIG_TSEC_ENET */ 317 318 /* 319 * Environment 320 */ 321 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 322 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 323 #define CONFIG_ENV_SIZE 0x2000 324 325 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 326 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 327 328 /* 329 * BOOTP options 330 */ 331 #define CONFIG_BOOTP_BOOTFILESIZE 332 333 #undef CONFIG_WATCHDOG /* watchdog disabled */ 334 335 /* 336 * Miscellaneous configurable options 337 */ 338 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 339 340 /* 341 * For booting Linux, the board info and command line data 342 * have to be in the first 64 MB of memory, since this is 343 * the maximum mapped by the Linux kernel during initialization. 344 */ 345 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 346 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 347 348 #if defined(CONFIG_CMD_KGDB) 349 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 350 #endif 351 352 /* 353 * Environment Configuration 354 */ 355 356 /* The mac addresses for all ethernet interface */ 357 #if defined(CONFIG_TSEC_ENET) 358 #define CONFIG_HAS_ETH0 359 #define CONFIG_HAS_ETH1 360 #define CONFIG_HAS_ETH2 361 #endif 362 363 #define CONFIG_IPADDR 192.168.1.253 364 365 #define CONFIG_HOSTNAME "unknown" 366 #define CONFIG_ROOTPATH "/nfsroot" 367 #define CONFIG_BOOTFILE "your.uImage" 368 369 #define CONFIG_SERVERIP 192.168.1.1 370 #define CONFIG_GATEWAYIP 192.168.1.1 371 #define CONFIG_NETMASK 255.255.255.0 372 373 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 374 375 #define CONFIG_EXTRA_ENV_SETTINGS \ 376 "netdev=eth0\0" \ 377 "consoledev=ttyS1\0" \ 378 "ramdiskaddr=600000\0" \ 379 "ramdiskfile=your.ramdisk.u-boot\0" \ 380 "fdtaddr=400000\0" \ 381 "fdtfile=your.fdt.dtb\0" 382 383 #define CONFIG_NFSBOOTCOMMAND \ 384 "setenv bootargs root=/dev/nfs rw " \ 385 "nfsroot=$serverip:$rootpath " \ 386 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 387 "console=$consoledev,$baudrate $othbootargs;" \ 388 "tftp $loadaddr $bootfile;" \ 389 "tftp $fdtaddr $fdtfile;" \ 390 "bootm $loadaddr - $fdtaddr" 391 392 #define CONFIG_RAMBOOTCOMMAND \ 393 "setenv bootargs root=/dev/ram rw " \ 394 "console=$consoledev,$baudrate $othbootargs;" \ 395 "tftp $ramdiskaddr $ramdiskfile;" \ 396 "tftp $loadaddr $bootfile;" \ 397 "bootm $loadaddr $ramdiskaddr" 398 399 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 400 401 #endif /* __CONFIG_H */ 402