1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8541cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 36 #define CONFIG_CPM2 1 /* has CPM2 */ 37 #define CONFIG_MPC8541 1 /* MPC8541 specific */ 38 #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ 39 40 #define CONFIG_PCI 41 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 42 #define CONFIG_ENV_OVERWRITE 43 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 44 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 45 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 46 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 47 48 /* 49 * When initializing flash, if we cannot find the manufacturer ID, 50 * assume this is the AMD flash associated with the CDS board. 51 * This allows booting from a promjet. 52 */ 53 #define CONFIG_ASSUME_AMD_FLASH 54 55 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 56 57 #ifndef __ASSEMBLY__ 58 extern unsigned long get_clock_freq(void); 59 #endif 60 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 61 62 /* 63 * These can be toggled for performance analysis, otherwise use default. 64 */ 65 #define CONFIG_L2_CACHE /* toggle L2 cache */ 66 #define CONFIG_BTB /* toggle branch predition */ 67 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 68 69 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 70 71 #undef CFG_DRAM_TEST /* memory test, takes time */ 72 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 73 #define CFG_MEMTEST_END 0x00400000 74 75 /* 76 * Base addresses -- Note these are effective addresses where the 77 * actual resources get mapped (not physical addresses) 78 */ 79 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 80 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 81 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 82 83 /* 84 * DDR Setup 85 */ 86 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 87 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 88 89 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 90 91 /* 92 * Make sure required options are set 93 */ 94 #ifndef CONFIG_SPD_EEPROM 95 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 96 #endif 97 98 /* 99 * SDRAM on the Local Bus 100 */ 101 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 102 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 103 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 104 105 #define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */ 106 #define CFG_BR1_PRELIM 0xff001001 /* port size 16bit */ 107 108 #define CFG_OR0_PRELIM 0xff806e61 /* 8MB Flash */ 109 #define CFG_OR1_PRELIM 0xff806e61 /* 8MB Flash */ 110 111 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} 112 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 113 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 114 #undef CFG_FLASH_CHECKSUM 115 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 116 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 117 118 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 119 120 #define CFG_FLASH_CFI_DRIVER 121 #define CFG_FLASH_CFI 122 #define CFG_FLASH_EMPTY_INFO 123 124 #undef CONFIG_CLOCKS_IN_MHZ 125 126 /* 127 * Local Bus Definitions 128 */ 129 130 /* 131 * Base Register 2 and Option Register 2 configure SDRAM. 132 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 133 * 134 * For BR2, need: 135 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 136 * port-size = 32-bits = BR2[19:20] = 11 137 * no parity checking = BR2[21:22] = 00 138 * SDRAM for MSEL = BR2[24:26] = 011 139 * Valid = BR[31] = 1 140 * 141 * 0 4 8 12 16 20 24 28 142 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 143 * 144 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 145 * FIXME: the top 17 bits of BR2. 146 */ 147 148 #define CFG_BR2_PRELIM 0xf0001861 149 150 /* 151 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 152 * 153 * For OR2, need: 154 * 64MB mask for AM, OR2[0:7] = 1111 1100 155 * XAM, OR2[17:18] = 11 156 * 9 columns OR2[19-21] = 010 157 * 13 rows OR2[23-25] = 100 158 * EAD set for extra time OR[31] = 1 159 * 160 * 0 4 8 12 16 20 24 28 161 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 162 */ 163 164 #define CFG_OR2_PRELIM 0xfc006901 165 166 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 167 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 168 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 169 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 170 171 /* 172 * LSDMR masks 173 */ 174 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 175 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 176 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 177 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 178 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 179 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 180 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 181 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 182 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 183 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 184 185 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 186 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 187 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 188 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 189 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 190 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 191 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 192 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 193 194 /* 195 * Common settings for all Local Bus SDRAM commands. 196 * At run time, either BSMA1516 (for CPU 1.1) 197 * or BSMA1617 (for CPU 1.0) (old) 198 * is OR'ed in too. 199 */ 200 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 201 | CFG_LBC_LSDMR_PRETOACT7 \ 202 | CFG_LBC_LSDMR_ACTTORW7 \ 203 | CFG_LBC_LSDMR_BL8 \ 204 | CFG_LBC_LSDMR_WRC4 \ 205 | CFG_LBC_LSDMR_CL3 \ 206 | CFG_LBC_LSDMR_RFEN \ 207 ) 208 209 /* 210 * The CADMUS registers are connected to CS3 on CDS. 211 * The new memory map places CADMUS at 0xf8000000. 212 * 213 * For BR3, need: 214 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 215 * port-size = 8-bits = BR[19:20] = 01 216 * no parity checking = BR[21:22] = 00 217 * GPMC for MSEL = BR[24:26] = 000 218 * Valid = BR[31] = 1 219 * 220 * 0 4 8 12 16 20 24 28 221 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 222 * 223 * For OR3, need: 224 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 225 * disable buffer ctrl OR[19] = 0 226 * CSNT OR[20] = 1 227 * ACS OR[21:22] = 11 228 * XACS OR[23] = 1 229 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 230 * SETA OR[28] = 0 231 * TRLX OR[29] = 1 232 * EHTR OR[30] = 1 233 * EAD extra time OR[31] = 1 234 * 235 * 0 4 8 12 16 20 24 28 236 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 237 */ 238 239 #define CADMUS_BASE_ADDR 0xf8000000 240 #define CFG_BR3_PRELIM 0xf8000801 241 #define CFG_OR3_PRELIM 0xfff00ff7 242 243 #define CONFIG_L1_INIT_RAM 244 #define CFG_INIT_RAM_LOCK 1 245 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 246 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 247 248 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 249 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 250 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 251 252 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 253 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 254 255 /* Serial Port */ 256 #define CONFIG_CONS_INDEX 2 257 #undef CONFIG_SERIAL_SOFTWARE_FIFO 258 #define CFG_NS16550 259 #define CFG_NS16550_SERIAL 260 #define CFG_NS16550_REG_SIZE 1 261 #define CFG_NS16550_CLK get_bus_freq(0) 262 263 #define CFG_BAUDRATE_TABLE \ 264 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 265 266 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 267 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 268 269 /* Use the HUSH parser */ 270 #define CFG_HUSH_PARSER 271 #ifdef CFG_HUSH_PARSER 272 #define CFG_PROMPT_HUSH_PS2 "> " 273 #endif 274 275 /* I2C */ 276 #define CONFIG_HARD_I2C /* I2C with hardware support */ 277 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 278 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 279 #define CFG_I2C_EEPROM_ADDR 0x57 280 #define CFG_I2C_SLAVE 0x7F 281 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 282 283 /* 284 * General PCI 285 * Addresses are mapped 1-1. 286 */ 287 #define CFG_PCI1_MEM_BASE 0x80000000 288 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 289 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 290 #define CFG_PCI1_IO_BASE 0xe2000000 291 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 292 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 293 294 #define CFG_PCI2_MEM_BASE 0xa0000000 295 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 296 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 297 #define CFG_PCI2_IO_BASE 0xe3000000 298 #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE 299 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ 300 301 302 #if defined(CONFIG_PCI) 303 304 #define CONFIG_NET_MULTI 305 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 306 307 #undef CONFIG_EEPRO100 308 #undef CONFIG_TULIP 309 310 #if !defined(CONFIG_PCI_PNP) 311 #define PCI_ENET0_IOADDR 0xe0000000 312 #define PCI_ENET0_MEMADDR 0xe0000000 313 #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ 314 #endif 315 316 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 317 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 318 319 #endif /* CONFIG_PCI */ 320 321 322 #if defined(CONFIG_TSEC_ENET) 323 324 #ifndef CONFIG_NET_MULTI 325 #define CONFIG_NET_MULTI 1 326 #endif 327 328 #define CONFIG_MII 1 /* MII PHY management */ 329 #define CONFIG_MPC85XX_TSEC1 1 330 #define CONFIG_MPC85XX_TSEC2 1 331 #undef CONFIG_MPC85XX_FEC 332 #define TSEC1_PHY_ADDR 0 333 #define TSEC2_PHY_ADDR 1 334 #define FEC_PHY_ADDR 3 335 #define TSEC1_PHYIDX 0 336 #define TSEC2_PHYIDX 0 337 #define FEC_PHYIDX 0 338 #define CONFIG_ETHPRIME "MOTO ENET0" 339 340 #endif /* CONFIG_TSEC_ENET */ 341 342 /* 343 * Environment 344 */ 345 #define CFG_ENV_IS_IN_FLASH 1 346 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 347 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 348 #define CFG_ENV_SIZE 0x2000 349 350 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 351 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 352 353 #if defined(CONFIG_PCI) 354 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 355 | CFG_CMD_PCI \ 356 | CFG_CMD_PING \ 357 | CFG_CMD_I2C \ 358 | CFG_CMD_MII) 359 #else 360 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 361 | CFG_CMD_PING \ 362 | CFG_CMD_I2C \ 363 | CFG_CMD_MII) 364 #endif 365 #include <cmd_confdefs.h> 366 367 #undef CONFIG_WATCHDOG /* watchdog disabled */ 368 369 /* 370 * Miscellaneous configurable options 371 */ 372 #define CFG_LONGHELP /* undef to save memory */ 373 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 374 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 375 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 376 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 377 #else 378 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 379 #endif 380 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 381 #define CFG_MAXARGS 16 /* max number of command args */ 382 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 383 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 384 385 /* 386 * For booting Linux, the board info and command line data 387 * have to be in the first 8 MB of memory, since this is 388 * the maximum mapped by the Linux kernel during initialization. 389 */ 390 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 391 392 /* Cache Configuration */ 393 #define CFG_DCACHE_SIZE 32768 394 #define CFG_CACHELINE_SIZE 32 395 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 396 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 397 #endif 398 399 /* 400 * Internal Definitions 401 * 402 * Boot Flags 403 */ 404 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 405 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 406 407 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 408 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 409 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 410 #endif 411 412 /* 413 * Environment Configuration 414 */ 415 416 /* The mac addresses for all ethernet interface */ 417 #if defined(CONFIG_TSEC_ENET) 418 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 419 #define CONFIG_HAS_ETH1 420 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 421 #define CONFIG_HAS_ETH2 422 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 423 #endif 424 425 #define CONFIG_IPADDR 192.168.1.253 426 427 #define CONFIG_HOSTNAME unknown 428 #define CONFIG_ROOTPATH /nfsroot 429 #define CONFIG_BOOTFILE your.uImage 430 431 #define CONFIG_SERVERIP 192.168.1.1 432 #define CONFIG_GATEWAYIP 192.168.1.1 433 #define CONFIG_NETMASK 255.255.255.0 434 435 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 436 437 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 438 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 439 440 #define CONFIG_BAUDRATE 115200 441 442 #define CONFIG_EXTRA_ENV_SETTINGS \ 443 "netdev=eth0\0" \ 444 "consoledev=ttyS1\0" \ 445 "ramdiskaddr=400000\0" \ 446 "ramdiskfile=your.ramdisk.u-boot\0" 447 448 #define CONFIG_NFSBOOTCOMMAND \ 449 "setenv bootargs root=/dev/nfs rw " \ 450 "nfsroot=$serverip:$rootpath " \ 451 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 452 "console=$consoledev,$baudrate $othbootargs;" \ 453 "tftp $loadaddr $bootfile;" \ 454 "bootm $loadaddr" 455 456 #define CONFIG_RAMBOOTCOMMAND \ 457 "setenv bootargs root=/dev/ram rw " \ 458 "console=$consoledev,$baudrate $othbootargs;" \ 459 "tftp $ramdiskaddr $ramdiskfile;" \ 460 "tftp $loadaddr $bootfile;" \ 461 "bootm $loadaddr $ramdiskaddr" 462 463 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 464 465 #endif /* __CONFIG_H */ 466