1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8541cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_CPM2 1 /* has CPM2 */ 18 19 #define CONFIG_PCI_INDIRECT_BRIDGE 20 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 21 #define CONFIG_ENV_OVERWRITE 22 23 #define CONFIG_FSL_VIA 24 25 #ifndef __ASSEMBLY__ 26 extern unsigned long get_clock_freq(void); 27 #endif 28 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 29 30 /* 31 * These can be toggled for performance analysis, otherwise use default. 32 */ 33 #define CONFIG_L2_CACHE /* toggle L2 cache */ 34 #define CONFIG_BTB /* toggle branch predition */ 35 36 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 37 #define CONFIG_SYS_MEMTEST_END 0x00400000 38 39 #define CONFIG_SYS_CCSRBAR 0xe0000000 40 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 41 42 /* DDR Setup */ 43 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 44 #define CONFIG_DDR_SPD 45 #undef CONFIG_FSL_DDR_INTERACTIVE 46 47 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 48 49 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 50 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 51 52 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 53 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 54 55 /* I2C addresses of SPD EEPROMs */ 56 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 57 58 /* 59 * Make sure required options are set 60 */ 61 #ifndef CONFIG_SPD_EEPROM 62 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 63 #endif 64 65 #undef CONFIG_CLOCKS_IN_MHZ 66 67 /* 68 * Local Bus Definitions 69 */ 70 71 /* 72 * FLASH on the Local Bus 73 * Two banks, 8M each, using the CFI driver. 74 * Boot from BR0/OR0 bank at 0xff00_0000 75 * Alternate BR1/OR1 bank at 0xff80_0000 76 * 77 * BR0, BR1: 78 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 79 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 80 * Port Size = 16 bits = BRx[19:20] = 10 81 * Use GPCM = BRx[24:26] = 000 82 * Valid = BRx[31] = 1 83 * 84 * 0 4 8 12 16 20 24 28 85 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 86 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 87 * 88 * OR0, OR1: 89 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 90 * Reserved ORx[17:18] = 11, confusion here? 91 * CSNT = ORx[20] = 1 92 * ACS = half cycle delay = ORx[21:22] = 11 93 * SCY = 6 = ORx[24:27] = 0110 94 * TRLX = use relaxed timing = ORx[29] = 1 95 * EAD = use external address latch delay = OR[31] = 1 96 * 97 * 0 4 8 12 16 20 24 28 98 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 99 */ 100 101 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 102 103 #define CONFIG_SYS_BR0_PRELIM 0xff801001 104 #define CONFIG_SYS_BR1_PRELIM 0xff001001 105 106 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 107 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 108 109 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 110 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 111 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 112 #undef CONFIG_SYS_FLASH_CHECKSUM 113 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 114 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 115 116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 117 118 #define CONFIG_FLASH_CFI_DRIVER 119 #define CONFIG_SYS_FLASH_CFI 120 #define CONFIG_SYS_FLASH_EMPTY_INFO 121 122 /* 123 * SDRAM on the Local Bus 124 */ 125 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 126 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 127 128 /* 129 * Base Register 2 and Option Register 2 configure SDRAM. 130 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 131 * 132 * For BR2, need: 133 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 134 * port-size = 32-bits = BR2[19:20] = 11 135 * no parity checking = BR2[21:22] = 00 136 * SDRAM for MSEL = BR2[24:26] = 011 137 * Valid = BR[31] = 1 138 * 139 * 0 4 8 12 16 20 24 28 140 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 141 * 142 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 143 * FIXME: the top 17 bits of BR2. 144 */ 145 146 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 147 148 /* 149 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 150 * 151 * For OR2, need: 152 * 64MB mask for AM, OR2[0:7] = 1111 1100 153 * XAM, OR2[17:18] = 11 154 * 9 columns OR2[19-21] = 010 155 * 13 rows OR2[23-25] = 100 156 * EAD set for extra time OR[31] = 1 157 * 158 * 0 4 8 12 16 20 24 28 159 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 160 */ 161 162 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 163 164 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 165 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 166 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 167 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 168 169 /* 170 * Common settings for all Local Bus SDRAM commands. 171 * At run time, either BSMA1516 (for CPU 1.1) 172 * or BSMA1617 (for CPU 1.0) (old) 173 * is OR'ed in too. 174 */ 175 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 176 | LSDMR_PRETOACT7 \ 177 | LSDMR_ACTTORW7 \ 178 | LSDMR_BL8 \ 179 | LSDMR_WRC4 \ 180 | LSDMR_CL3 \ 181 | LSDMR_RFEN \ 182 ) 183 184 /* 185 * The CADMUS registers are connected to CS3 on CDS. 186 * The new memory map places CADMUS at 0xf8000000. 187 * 188 * For BR3, need: 189 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 190 * port-size = 8-bits = BR[19:20] = 01 191 * no parity checking = BR[21:22] = 00 192 * GPMC for MSEL = BR[24:26] = 000 193 * Valid = BR[31] = 1 194 * 195 * 0 4 8 12 16 20 24 28 196 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 197 * 198 * For OR3, need: 199 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 200 * disable buffer ctrl OR[19] = 0 201 * CSNT OR[20] = 1 202 * ACS OR[21:22] = 11 203 * XACS OR[23] = 1 204 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 205 * SETA OR[28] = 0 206 * TRLX OR[29] = 1 207 * EHTR OR[30] = 1 208 * EAD extra time OR[31] = 1 209 * 210 * 0 4 8 12 16 20 24 28 211 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 212 */ 213 214 #define CONFIG_FSL_CADMUS 215 216 #define CADMUS_BASE_ADDR 0xf8000000 217 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 218 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 219 220 #define CONFIG_SYS_INIT_RAM_LOCK 1 221 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 222 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 223 224 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 225 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 226 227 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 228 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 229 230 /* Serial Port */ 231 #define CONFIG_SYS_NS16550_SERIAL 232 #define CONFIG_SYS_NS16550_REG_SIZE 1 233 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 234 235 #define CONFIG_SYS_BAUDRATE_TABLE \ 236 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 237 238 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 239 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 240 241 /* 242 * I2C 243 */ 244 #define CONFIG_SYS_I2C 245 #define CONFIG_SYS_I2C_FSL 246 #define CONFIG_SYS_FSL_I2C_SPEED 400000 247 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 248 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 249 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 250 251 /* EEPROM */ 252 #define CONFIG_ID_EEPROM 253 #define CONFIG_SYS_I2C_EEPROM_CCID 254 #define CONFIG_SYS_ID_EEPROM 255 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 256 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 257 258 /* 259 * General PCI 260 * Memory space is mapped 1-1, but I/O space must start from 0. 261 */ 262 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 263 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 264 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 265 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 266 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 267 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 268 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 269 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 270 271 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 272 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 273 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 274 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 275 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 276 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 277 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 278 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ 279 280 #ifdef CONFIG_LEGACY 281 #define BRIDGE_ID 17 282 #define VIA_ID 2 283 #else 284 #define BRIDGE_ID 28 285 #define VIA_ID 4 286 #endif 287 288 #if defined(CONFIG_PCI) 289 290 #define CONFIG_MPC85XX_PCI2 291 292 #undef CONFIG_EEPRO100 293 #undef CONFIG_TULIP 294 295 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 296 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 297 298 #endif /* CONFIG_PCI */ 299 300 #if defined(CONFIG_TSEC_ENET) 301 302 #define CONFIG_MII 1 /* MII PHY management */ 303 #define CONFIG_TSEC1 1 304 #define CONFIG_TSEC1_NAME "TSEC0" 305 #define CONFIG_TSEC2 1 306 #define CONFIG_TSEC2_NAME "TSEC1" 307 #define TSEC1_PHY_ADDR 0 308 #define TSEC2_PHY_ADDR 1 309 #define TSEC1_PHYIDX 0 310 #define TSEC2_PHYIDX 0 311 #define TSEC1_FLAGS TSEC_GIGABIT 312 #define TSEC2_FLAGS TSEC_GIGABIT 313 314 /* Options are: TSEC[0-1] */ 315 #define CONFIG_ETHPRIME "TSEC0" 316 317 #endif /* CONFIG_TSEC_ENET */ 318 319 /* 320 * Environment 321 */ 322 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 323 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 324 #define CONFIG_ENV_SIZE 0x2000 325 326 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 327 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 328 329 /* 330 * BOOTP options 331 */ 332 #define CONFIG_BOOTP_BOOTFILESIZE 333 334 #undef CONFIG_WATCHDOG /* watchdog disabled */ 335 336 /* 337 * Miscellaneous configurable options 338 */ 339 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 340 341 /* 342 * For booting Linux, the board info and command line data 343 * have to be in the first 64 MB of memory, since this is 344 * the maximum mapped by the Linux kernel during initialization. 345 */ 346 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 347 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 348 349 #if defined(CONFIG_CMD_KGDB) 350 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 351 #endif 352 353 /* 354 * Environment Configuration 355 */ 356 357 /* The mac addresses for all ethernet interface */ 358 #if defined(CONFIG_TSEC_ENET) 359 #define CONFIG_HAS_ETH0 360 #define CONFIG_HAS_ETH1 361 #define CONFIG_HAS_ETH2 362 #endif 363 364 #define CONFIG_IPADDR 192.168.1.253 365 366 #define CONFIG_HOSTNAME "unknown" 367 #define CONFIG_ROOTPATH "/nfsroot" 368 #define CONFIG_BOOTFILE "your.uImage" 369 370 #define CONFIG_SERVERIP 192.168.1.1 371 #define CONFIG_GATEWAYIP 192.168.1.1 372 #define CONFIG_NETMASK 255.255.255.0 373 374 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 375 376 #define CONFIG_EXTRA_ENV_SETTINGS \ 377 "netdev=eth0\0" \ 378 "consoledev=ttyS1\0" \ 379 "ramdiskaddr=600000\0" \ 380 "ramdiskfile=your.ramdisk.u-boot\0" \ 381 "fdtaddr=400000\0" \ 382 "fdtfile=your.fdt.dtb\0" 383 384 #define CONFIG_NFSBOOTCOMMAND \ 385 "setenv bootargs root=/dev/nfs rw " \ 386 "nfsroot=$serverip:$rootpath " \ 387 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 388 "console=$consoledev,$baudrate $othbootargs;" \ 389 "tftp $loadaddr $bootfile;" \ 390 "tftp $fdtaddr $fdtfile;" \ 391 "bootm $loadaddr - $fdtaddr" 392 393 #define CONFIG_RAMBOOTCOMMAND \ 394 "setenv bootargs root=/dev/ram rw " \ 395 "console=$consoledev,$baudrate $othbootargs;" \ 396 "tftp $ramdiskaddr $ramdiskfile;" \ 397 "tftp $loadaddr $bootfile;" \ 398 "bootm $loadaddr $ramdiskaddr" 399 400 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 401 402 #endif /* __CONFIG_H */ 403