1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8541cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 36 #define CONFIG_MPC8541 1 /* MPC8541 specific */ 37 #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ 38 39 #define CONFIG_PCI 40 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 41 #define CONFIG_ENV_OVERWRITE 42 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 43 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 44 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 45 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 46 47 /* 48 * When initializing flash, if we cannot find the manufacturer ID, 49 * assume this is the AMD flash associated with the CDS board. 50 * This allows booting from a promjet. 51 */ 52 #define CONFIG_ASSUME_AMD_FLASH 53 54 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 55 56 #ifndef __ASSEMBLY__ 57 extern unsigned long get_clock_freq(void); 58 #endif 59 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 60 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_L2_CACHE /* toggle L2 cache */ 65 #define CONFIG_BTB /* toggle branch predition */ 66 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 67 68 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 69 70 #undef CFG_DRAM_TEST /* memory test, takes time */ 71 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 72 #define CFG_MEMTEST_END 0x00400000 73 74 /* 75 * Base addresses -- Note these are effective addresses where the 76 * actual resources get mapped (not physical addresses) 77 */ 78 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 79 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 80 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 81 82 /* 83 * DDR Setup 84 */ 85 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 86 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 87 88 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 89 90 /* 91 * Make sure required options are set 92 */ 93 #ifndef CONFIG_SPD_EEPROM 94 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 95 #endif 96 97 /* 98 * SDRAM on the Local Bus 99 */ 100 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 101 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 102 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 103 104 #define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */ 105 #define CFG_BR1_PRELIM 0xff001001 /* port size 16bit */ 106 107 #define CFG_OR0_PRELIM 0xff806e61 /* 8MB Flash */ 108 #define CFG_OR1_PRELIM 0xff806e61 /* 8MB Flash */ 109 110 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} 111 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 112 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 113 #undef CFG_FLASH_CHECKSUM 114 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 115 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 116 117 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 118 119 #define CFG_FLASH_CFI_DRIVER 120 #define CFG_FLASH_CFI 121 #define CFG_FLASH_EMPTY_INFO 122 123 #undef CONFIG_CLOCKS_IN_MHZ 124 125 /* 126 * Local Bus Definitions 127 */ 128 129 /* 130 * Base Register 2 and Option Register 2 configure SDRAM. 131 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 132 * 133 * For BR2, need: 134 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 135 * port-size = 32-bits = BR2[19:20] = 11 136 * no parity checking = BR2[21:22] = 00 137 * SDRAM for MSEL = BR2[24:26] = 011 138 * Valid = BR[31] = 1 139 * 140 * 0 4 8 12 16 20 24 28 141 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 142 * 143 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 144 * FIXME: the top 17 bits of BR2. 145 */ 146 147 #define CFG_BR2_PRELIM 0xf0001861 148 149 /* 150 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 151 * 152 * For OR2, need: 153 * 64MB mask for AM, OR2[0:7] = 1111 1100 154 * XAM, OR2[17:18] = 11 155 * 9 columns OR2[19-21] = 010 156 * 13 rows OR2[23-25] = 100 157 * EAD set for extra time OR[31] = 1 158 * 159 * 0 4 8 12 16 20 24 28 160 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 161 */ 162 163 #define CFG_OR2_PRELIM 0xfc006901 164 165 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 166 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 167 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 168 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 169 170 /* 171 * LSDMR masks 172 */ 173 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 174 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 175 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 176 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 177 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 178 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 179 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 180 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 181 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 182 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 183 184 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 185 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 186 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 187 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 188 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 189 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 190 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 191 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 192 193 /* 194 * Common settings for all Local Bus SDRAM commands. 195 * At run time, either BSMA1516 (for CPU 1.1) 196 * or BSMA1617 (for CPU 1.0) (old) 197 * is OR'ed in too. 198 */ 199 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 200 | CFG_LBC_LSDMR_PRETOACT7 \ 201 | CFG_LBC_LSDMR_ACTTORW7 \ 202 | CFG_LBC_LSDMR_BL8 \ 203 | CFG_LBC_LSDMR_WRC4 \ 204 | CFG_LBC_LSDMR_CL3 \ 205 | CFG_LBC_LSDMR_RFEN \ 206 ) 207 208 /* 209 * The CADMUS registers are connected to CS3 on CDS. 210 * The new memory map places CADMUS at 0xf8000000. 211 * 212 * For BR3, need: 213 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 214 * port-size = 8-bits = BR[19:20] = 01 215 * no parity checking = BR[21:22] = 00 216 * GPMC for MSEL = BR[24:26] = 000 217 * Valid = BR[31] = 1 218 * 219 * 0 4 8 12 16 20 24 28 220 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 221 * 222 * For OR3, need: 223 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 224 * disable buffer ctrl OR[19] = 0 225 * CSNT OR[20] = 1 226 * ACS OR[21:22] = 11 227 * XACS OR[23] = 1 228 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 229 * SETA OR[28] = 0 230 * TRLX OR[29] = 1 231 * EHTR OR[30] = 1 232 * EAD extra time OR[31] = 1 233 * 234 * 0 4 8 12 16 20 24 28 235 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 236 */ 237 238 #define CADMUS_BASE_ADDR 0xf8000000 239 #define CFG_BR3_PRELIM 0xf8000801 240 #define CFG_OR3_PRELIM 0xfff00ff7 241 242 #define CONFIG_L1_INIT_RAM 243 #define CFG_INIT_RAM_LOCK 1 244 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 245 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 246 247 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 248 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 249 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 250 251 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 252 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 253 254 /* Serial Port */ 255 #define CONFIG_CONS_INDEX 2 256 #undef CONFIG_SERIAL_SOFTWARE_FIFO 257 #define CFG_NS16550 258 #define CFG_NS16550_SERIAL 259 #define CFG_NS16550_REG_SIZE 1 260 #define CFG_NS16550_CLK get_bus_freq(0) 261 262 #define CFG_BAUDRATE_TABLE \ 263 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 264 265 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 266 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 267 268 /* Use the HUSH parser */ 269 #define CFG_HUSH_PARSER 270 #ifdef CFG_HUSH_PARSER 271 #define CFG_PROMPT_HUSH_PS2 "> " 272 #endif 273 274 /* I2C */ 275 #define CONFIG_HARD_I2C /* I2C with hardware support */ 276 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 277 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 278 #define CFG_I2C_EEPROM_ADDR 0x57 279 #define CFG_I2C_SLAVE 0x7F 280 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 281 282 /* 283 * General PCI 284 * Addresses are mapped 1-1. 285 */ 286 #define CFG_PCI1_MEM_BASE 0x80000000 287 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 288 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 289 #define CFG_PCI1_IO_BASE 0xe2000000 290 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 291 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 292 293 #define CFG_PCI2_MEM_BASE 0xa0000000 294 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 295 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 296 #define CFG_PCI2_IO_BASE 0xe3000000 297 #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE 298 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ 299 300 301 #if defined(CONFIG_PCI) 302 303 #define CONFIG_NET_MULTI 304 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 305 306 #undef CONFIG_EEPRO100 307 #undef CONFIG_TULIP 308 309 #if !defined(CONFIG_PCI_PNP) 310 #define PCI_ENET0_IOADDR 0xe0000000 311 #define PCI_ENET0_MEMADDR 0xe0000000 312 #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ 313 #endif 314 315 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 316 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 317 318 #endif /* CONFIG_PCI */ 319 320 321 #if defined(CONFIG_TSEC_ENET) 322 323 #ifndef CONFIG_NET_MULTI 324 #define CONFIG_NET_MULTI 1 325 #endif 326 327 #define CONFIG_MII 1 /* MII PHY management */ 328 #define CONFIG_MPC85XX_TSEC1 1 329 #define CONFIG_MPC85XX_TSEC2 1 330 #undef CONFIG_MPC85XX_FEC 331 #define TSEC1_PHY_ADDR 0 332 #define TSEC2_PHY_ADDR 1 333 #define FEC_PHY_ADDR 3 334 #define TSEC1_PHYIDX 0 335 #define TSEC2_PHYIDX 0 336 #define FEC_PHYIDX 0 337 #define CONFIG_ETHPRIME "MOTO ENET0" 338 339 #endif /* CONFIG_TSEC_ENET */ 340 341 /* 342 * Environment 343 */ 344 #define CFG_ENV_IS_IN_FLASH 1 345 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 346 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 347 #define CFG_ENV_SIZE 0x2000 348 349 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 350 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 351 352 #if defined(CONFIG_PCI) 353 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 354 | CFG_CMD_PCI \ 355 | CFG_CMD_PING \ 356 | CFG_CMD_I2C \ 357 | CFG_CMD_MII) 358 #else 359 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 360 | CFG_CMD_PING \ 361 | CFG_CMD_I2C \ 362 | CFG_CMD_MII) 363 #endif 364 #include <cmd_confdefs.h> 365 366 #undef CONFIG_WATCHDOG /* watchdog disabled */ 367 368 /* 369 * Miscellaneous configurable options 370 */ 371 #define CFG_LONGHELP /* undef to save memory */ 372 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 373 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 374 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 375 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 376 #else 377 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 378 #endif 379 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 380 #define CFG_MAXARGS 16 /* max number of command args */ 381 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 382 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 383 384 /* 385 * For booting Linux, the board info and command line data 386 * have to be in the first 8 MB of memory, since this is 387 * the maximum mapped by the Linux kernel during initialization. 388 */ 389 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 390 391 /* Cache Configuration */ 392 #define CFG_DCACHE_SIZE 32768 393 #define CFG_CACHELINE_SIZE 32 394 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 395 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 396 #endif 397 398 /* 399 * Internal Definitions 400 * 401 * Boot Flags 402 */ 403 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 404 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 405 406 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 407 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 408 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 409 #endif 410 411 /* 412 * Environment Configuration 413 */ 414 415 /* The mac addresses for all ethernet interface */ 416 #if defined(CONFIG_TSEC_ENET) 417 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 418 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 419 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 420 #endif 421 422 #define CONFIG_IPADDR 192.168.1.253 423 424 #define CONFIG_HOSTNAME unknown 425 #define CONFIG_ROOTPATH /nfsroot 426 #define CONFIG_BOOTFILE your.uImage 427 428 #define CONFIG_SERVERIP 192.168.1.1 429 #define CONFIG_GATEWAYIP 192.168.1.1 430 #define CONFIG_NETMASK 255.255.255.0 431 432 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 433 434 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 435 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 436 437 #define CONFIG_BAUDRATE 115200 438 439 #define CONFIG_EXTRA_ENV_SETTINGS \ 440 "netdev=eth0\0" \ 441 "consoledev=ttyS1\0" \ 442 "ramdiskaddr=400000\0" \ 443 "ramdiskfile=your.ramdisk.u-boot\0" 444 445 #define CONFIG_NFSBOOTCOMMAND \ 446 "setenv bootargs root=/dev/nfs rw " \ 447 "nfsroot=$serverip:$rootpath " \ 448 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 449 "console=$consoledev,$baudrate $othbootargs;" \ 450 "tftp $loadaddr $bootfile;" \ 451 "bootm $loadaddr" 452 453 #define CONFIG_RAMBOOTCOMMAND \ 454 "setenv bootargs root=/dev/ram rw " \ 455 "console=$consoledev,$baudrate $othbootargs;" \ 456 "tftp $ramdiskaddr $ramdiskfile;" \ 457 "tftp $loadaddr $bootfile;" \ 458 "bootm $loadaddr $ramdiskaddr" 459 460 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 461 462 #endif /* __CONFIG_H */ 463