1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8541cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 36 #define CONFIG_CPM2 1 /* has CPM2 */ 37 #define CONFIG_MPC8541 1 /* MPC8541 specific */ 38 #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ 39 40 #define CONFIG_PCI 41 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 42 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 43 #define CONFIG_ENV_OVERWRITE 44 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_FSL_VIA 48 49 /* 50 * When initializing flash, if we cannot find the manufacturer ID, 51 * assume this is the AMD flash associated with the CDS board. 52 * This allows booting from a promjet. 53 */ 54 #define CONFIG_ASSUME_AMD_FLASH 55 56 #ifndef __ASSEMBLY__ 57 extern unsigned long get_clock_freq(void); 58 #endif 59 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 60 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_L2_CACHE /* toggle L2 cache */ 65 #define CONFIG_BTB /* toggle branch predition */ 66 67 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 68 #define CONFIG_SYS_MEMTEST_END 0x00400000 69 70 /* 71 * Base addresses -- Note these are effective addresses where the 72 * actual resources get mapped (not physical addresses) 73 */ 74 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 75 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 76 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 77 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 78 79 /* DDR Setup */ 80 #define CONFIG_FSL_DDR1 81 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 82 #define CONFIG_DDR_SPD 83 #undef CONFIG_FSL_DDR_INTERACTIVE 84 85 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 86 87 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 88 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 89 90 #define CONFIG_NUM_DDR_CONTROLLERS 1 91 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 92 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 93 94 /* I2C addresses of SPD EEPROMs */ 95 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 96 97 /* 98 * Make sure required options are set 99 */ 100 #ifndef CONFIG_SPD_EEPROM 101 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 102 #endif 103 104 #undef CONFIG_CLOCKS_IN_MHZ 105 106 /* 107 * Local Bus Definitions 108 */ 109 110 /* 111 * FLASH on the Local Bus 112 * Two banks, 8M each, using the CFI driver. 113 * Boot from BR0/OR0 bank at 0xff00_0000 114 * Alternate BR1/OR1 bank at 0xff80_0000 115 * 116 * BR0, BR1: 117 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 118 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 119 * Port Size = 16 bits = BRx[19:20] = 10 120 * Use GPCM = BRx[24:26] = 000 121 * Valid = BRx[31] = 1 122 * 123 * 0 4 8 12 16 20 24 28 124 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 125 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 126 * 127 * OR0, OR1: 128 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 129 * Reserved ORx[17:18] = 11, confusion here? 130 * CSNT = ORx[20] = 1 131 * ACS = half cycle delay = ORx[21:22] = 11 132 * SCY = 6 = ORx[24:27] = 0110 133 * TRLX = use relaxed timing = ORx[29] = 1 134 * EAD = use external address latch delay = OR[31] = 1 135 * 136 * 0 4 8 12 16 20 24 28 137 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 138 */ 139 140 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 141 142 #define CONFIG_SYS_BR0_PRELIM 0xff801001 143 #define CONFIG_SYS_BR1_PRELIM 0xff001001 144 145 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 146 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 147 148 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 149 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 150 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 151 #undef CONFIG_SYS_FLASH_CHECKSUM 152 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 153 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 154 155 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 156 157 #define CONFIG_FLASH_CFI_DRIVER 158 #define CONFIG_SYS_FLASH_CFI 159 #define CONFIG_SYS_FLASH_EMPTY_INFO 160 161 162 /* 163 * SDRAM on the Local Bus 164 */ 165 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 166 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 167 168 /* 169 * Base Register 2 and Option Register 2 configure SDRAM. 170 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 171 * 172 * For BR2, need: 173 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 174 * port-size = 32-bits = BR2[19:20] = 11 175 * no parity checking = BR2[21:22] = 00 176 * SDRAM for MSEL = BR2[24:26] = 011 177 * Valid = BR[31] = 1 178 * 179 * 0 4 8 12 16 20 24 28 180 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 181 * 182 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 183 * FIXME: the top 17 bits of BR2. 184 */ 185 186 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 187 188 /* 189 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 190 * 191 * For OR2, need: 192 * 64MB mask for AM, OR2[0:7] = 1111 1100 193 * XAM, OR2[17:18] = 11 194 * 9 columns OR2[19-21] = 010 195 * 13 rows OR2[23-25] = 100 196 * EAD set for extra time OR[31] = 1 197 * 198 * 0 4 8 12 16 20 24 28 199 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 200 */ 201 202 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 203 204 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 205 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 206 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 207 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 208 209 /* 210 * Common settings for all Local Bus SDRAM commands. 211 * At run time, either BSMA1516 (for CPU 1.1) 212 * or BSMA1617 (for CPU 1.0) (old) 213 * is OR'ed in too. 214 */ 215 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 216 | LSDMR_PRETOACT7 \ 217 | LSDMR_ACTTORW7 \ 218 | LSDMR_BL8 \ 219 | LSDMR_WRC4 \ 220 | LSDMR_CL3 \ 221 | LSDMR_RFEN \ 222 ) 223 224 /* 225 * The CADMUS registers are connected to CS3 on CDS. 226 * The new memory map places CADMUS at 0xf8000000. 227 * 228 * For BR3, need: 229 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 230 * port-size = 8-bits = BR[19:20] = 01 231 * no parity checking = BR[21:22] = 00 232 * GPMC for MSEL = BR[24:26] = 000 233 * Valid = BR[31] = 1 234 * 235 * 0 4 8 12 16 20 24 28 236 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 237 * 238 * For OR3, need: 239 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 240 * disable buffer ctrl OR[19] = 0 241 * CSNT OR[20] = 1 242 * ACS OR[21:22] = 11 243 * XACS OR[23] = 1 244 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 245 * SETA OR[28] = 0 246 * TRLX OR[29] = 1 247 * EHTR OR[30] = 1 248 * EAD extra time OR[31] = 1 249 * 250 * 0 4 8 12 16 20 24 28 251 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 252 */ 253 254 #define CONFIG_FSL_CADMUS 255 256 #define CADMUS_BASE_ADDR 0xf8000000 257 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 258 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 259 260 #define CONFIG_SYS_INIT_RAM_LOCK 1 261 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 262 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 263 264 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 265 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 266 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 267 268 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 269 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 270 271 /* Serial Port */ 272 #define CONFIG_CONS_INDEX 2 273 #undef CONFIG_SERIAL_SOFTWARE_FIFO 274 #define CONFIG_SYS_NS16550 275 #define CONFIG_SYS_NS16550_SERIAL 276 #define CONFIG_SYS_NS16550_REG_SIZE 1 277 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 278 279 #define CONFIG_SYS_BAUDRATE_TABLE \ 280 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 281 282 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 283 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 284 285 /* Use the HUSH parser */ 286 #define CONFIG_SYS_HUSH_PARSER 287 #ifdef CONFIG_SYS_HUSH_PARSER 288 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 289 #endif 290 291 /* pass open firmware flat tree */ 292 #define CONFIG_OF_LIBFDT 1 293 #define CONFIG_OF_BOARD_SETUP 1 294 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 295 296 #define CONFIG_SYS_64BIT_VSPRINTF 1 297 #define CONFIG_SYS_64BIT_STRTOUL 1 298 299 /* 300 * I2C 301 */ 302 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 303 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 304 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 305 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 306 #define CONFIG_SYS_I2C_SLAVE 0x7F 307 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 308 #define CONFIG_SYS_I2C_OFFSET 0x3000 309 310 /* EEPROM */ 311 #define CONFIG_ID_EEPROM 312 #define CONFIG_SYS_I2C_EEPROM_CCID 313 #define CONFIG_SYS_ID_EEPROM 314 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 315 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 316 317 /* 318 * General PCI 319 * Memory space is mapped 1-1, but I/O space must start from 0. 320 */ 321 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 322 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 323 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 324 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 325 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 326 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 327 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 328 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 329 330 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 331 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 332 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 333 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 334 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 335 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 336 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 337 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ 338 339 #ifdef CONFIG_LEGACY 340 #define BRIDGE_ID 17 341 #define VIA_ID 2 342 #else 343 #define BRIDGE_ID 28 344 #define VIA_ID 4 345 #endif 346 347 #if defined(CONFIG_PCI) 348 349 #define CONFIG_MPC85XX_PCI2 350 #define CONFIG_NET_MULTI 351 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 352 353 #undef CONFIG_EEPRO100 354 #undef CONFIG_TULIP 355 356 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 357 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 358 359 #endif /* CONFIG_PCI */ 360 361 362 #if defined(CONFIG_TSEC_ENET) 363 364 #ifndef CONFIG_NET_MULTI 365 #define CONFIG_NET_MULTI 1 366 #endif 367 368 #define CONFIG_MII 1 /* MII PHY management */ 369 #define CONFIG_TSEC1 1 370 #define CONFIG_TSEC1_NAME "TSEC0" 371 #define CONFIG_TSEC2 1 372 #define CONFIG_TSEC2_NAME "TSEC1" 373 #define TSEC1_PHY_ADDR 0 374 #define TSEC2_PHY_ADDR 1 375 #define TSEC1_PHYIDX 0 376 #define TSEC2_PHYIDX 0 377 #define TSEC1_FLAGS TSEC_GIGABIT 378 #define TSEC2_FLAGS TSEC_GIGABIT 379 380 /* Options are: TSEC[0-1] */ 381 #define CONFIG_ETHPRIME "TSEC0" 382 383 #endif /* CONFIG_TSEC_ENET */ 384 385 /* 386 * Environment 387 */ 388 #define CONFIG_ENV_IS_IN_FLASH 1 389 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 390 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 391 #define CONFIG_ENV_SIZE 0x2000 392 393 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 394 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 395 396 /* 397 * BOOTP options 398 */ 399 #define CONFIG_BOOTP_BOOTFILESIZE 400 #define CONFIG_BOOTP_BOOTPATH 401 #define CONFIG_BOOTP_GATEWAY 402 #define CONFIG_BOOTP_HOSTNAME 403 404 405 /* 406 * Command line configuration. 407 */ 408 #include <config_cmd_default.h> 409 410 #define CONFIG_CMD_PING 411 #define CONFIG_CMD_I2C 412 #define CONFIG_CMD_MII 413 #define CONFIG_CMD_ELF 414 #define CONFIG_CMD_IRQ 415 #define CONFIG_CMD_SETEXPR 416 417 #if defined(CONFIG_PCI) 418 #define CONFIG_CMD_PCI 419 #endif 420 421 422 #undef CONFIG_WATCHDOG /* watchdog disabled */ 423 424 /* 425 * Miscellaneous configurable options 426 */ 427 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 428 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 429 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 430 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 431 #if defined(CONFIG_CMD_KGDB) 432 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 433 #else 434 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 435 #endif 436 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 437 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 438 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 439 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 440 441 /* 442 * For booting Linux, the board info and command line data 443 * have to be in the first 8 MB of memory, since this is 444 * the maximum mapped by the Linux kernel during initialization. 445 */ 446 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 447 448 /* 449 * Internal Definitions 450 * 451 * Boot Flags 452 */ 453 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 454 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 455 456 #if defined(CONFIG_CMD_KGDB) 457 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 458 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 459 #endif 460 461 /* 462 * Environment Configuration 463 */ 464 465 /* The mac addresses for all ethernet interface */ 466 #if defined(CONFIG_TSEC_ENET) 467 #define CONFIG_HAS_ETH0 468 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 469 #define CONFIG_HAS_ETH1 470 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 471 #define CONFIG_HAS_ETH2 472 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 473 #endif 474 475 #define CONFIG_IPADDR 192.168.1.253 476 477 #define CONFIG_HOSTNAME unknown 478 #define CONFIG_ROOTPATH /nfsroot 479 #define CONFIG_BOOTFILE your.uImage 480 481 #define CONFIG_SERVERIP 192.168.1.1 482 #define CONFIG_GATEWAYIP 192.168.1.1 483 #define CONFIG_NETMASK 255.255.255.0 484 485 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 486 487 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 488 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 489 490 #define CONFIG_BAUDRATE 115200 491 492 #define CONFIG_EXTRA_ENV_SETTINGS \ 493 "netdev=eth0\0" \ 494 "consoledev=ttyS1\0" \ 495 "ramdiskaddr=600000\0" \ 496 "ramdiskfile=your.ramdisk.u-boot\0" \ 497 "fdtaddr=400000\0" \ 498 "fdtfile=your.fdt.dtb\0" 499 500 #define CONFIG_NFSBOOTCOMMAND \ 501 "setenv bootargs root=/dev/nfs rw " \ 502 "nfsroot=$serverip:$rootpath " \ 503 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 504 "console=$consoledev,$baudrate $othbootargs;" \ 505 "tftp $loadaddr $bootfile;" \ 506 "tftp $fdtaddr $fdtfile;" \ 507 "bootm $loadaddr - $fdtaddr" 508 509 #define CONFIG_RAMBOOTCOMMAND \ 510 "setenv bootargs root=/dev/ram rw " \ 511 "console=$consoledev,$baudrate $othbootargs;" \ 512 "tftp $ramdiskaddr $ramdiskfile;" \ 513 "tftp $loadaddr $bootfile;" \ 514 "bootm $loadaddr $ramdiskaddr" 515 516 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 517 518 #endif /* __CONFIG_H */ 519