1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8541cds board configuration file 8 * 9 * Please refer to doc/README.mpc85xxcds for more info. 10 * 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* High Level Configuration Options */ 16 #define CONFIG_CPM2 1 /* has CPM2 */ 17 18 #define CONFIG_PCI_INDIRECT_BRIDGE 19 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 20 #define CONFIG_ENV_OVERWRITE 21 22 #define CONFIG_FSL_VIA 23 24 #ifndef __ASSEMBLY__ 25 extern unsigned long get_clock_freq(void); 26 #endif 27 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 28 29 /* 30 * These can be toggled for performance analysis, otherwise use default. 31 */ 32 #define CONFIG_L2_CACHE /* toggle L2 cache */ 33 #define CONFIG_BTB /* toggle branch predition */ 34 35 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 36 #define CONFIG_SYS_MEMTEST_END 0x00400000 37 38 #define CONFIG_SYS_CCSRBAR 0xe0000000 39 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 40 41 /* DDR Setup */ 42 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 43 #define CONFIG_DDR_SPD 44 45 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 46 47 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 48 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 49 50 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 51 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 52 53 /* I2C addresses of SPD EEPROMs */ 54 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 55 56 /* 57 * Make sure required options are set 58 */ 59 #ifndef CONFIG_SPD_EEPROM 60 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 61 #endif 62 63 #undef CONFIG_CLOCKS_IN_MHZ 64 65 /* 66 * Local Bus Definitions 67 */ 68 69 /* 70 * FLASH on the Local Bus 71 * Two banks, 8M each, using the CFI driver. 72 * Boot from BR0/OR0 bank at 0xff00_0000 73 * Alternate BR1/OR1 bank at 0xff80_0000 74 * 75 * BR0, BR1: 76 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 77 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 78 * Port Size = 16 bits = BRx[19:20] = 10 79 * Use GPCM = BRx[24:26] = 000 80 * Valid = BRx[31] = 1 81 * 82 * 0 4 8 12 16 20 24 28 83 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 84 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 85 * 86 * OR0, OR1: 87 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 88 * Reserved ORx[17:18] = 11, confusion here? 89 * CSNT = ORx[20] = 1 90 * ACS = half cycle delay = ORx[21:22] = 11 91 * SCY = 6 = ORx[24:27] = 0110 92 * TRLX = use relaxed timing = ORx[29] = 1 93 * EAD = use external address latch delay = OR[31] = 1 94 * 95 * 0 4 8 12 16 20 24 28 96 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 97 */ 98 99 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 100 101 #define CONFIG_SYS_BR0_PRELIM 0xff801001 102 #define CONFIG_SYS_BR1_PRELIM 0xff001001 103 104 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 105 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 106 107 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 108 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 109 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 110 #undef CONFIG_SYS_FLASH_CHECKSUM 111 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 112 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 113 114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 115 116 #define CONFIG_SYS_FLASH_EMPTY_INFO 117 118 /* 119 * SDRAM on the Local Bus 120 */ 121 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 122 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 123 124 /* 125 * Base Register 2 and Option Register 2 configure SDRAM. 126 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 127 * 128 * For BR2, need: 129 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 130 * port-size = 32-bits = BR2[19:20] = 11 131 * no parity checking = BR2[21:22] = 00 132 * SDRAM for MSEL = BR2[24:26] = 011 133 * Valid = BR[31] = 1 134 * 135 * 0 4 8 12 16 20 24 28 136 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 137 * 138 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 139 * FIXME: the top 17 bits of BR2. 140 */ 141 142 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 143 144 /* 145 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 146 * 147 * For OR2, need: 148 * 64MB mask for AM, OR2[0:7] = 1111 1100 149 * XAM, OR2[17:18] = 11 150 * 9 columns OR2[19-21] = 010 151 * 13 rows OR2[23-25] = 100 152 * EAD set for extra time OR[31] = 1 153 * 154 * 0 4 8 12 16 20 24 28 155 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 156 */ 157 158 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 159 160 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 161 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 162 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 163 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 164 165 /* 166 * Common settings for all Local Bus SDRAM commands. 167 * At run time, either BSMA1516 (for CPU 1.1) 168 * or BSMA1617 (for CPU 1.0) (old) 169 * is OR'ed in too. 170 */ 171 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 172 | LSDMR_PRETOACT7 \ 173 | LSDMR_ACTTORW7 \ 174 | LSDMR_BL8 \ 175 | LSDMR_WRC4 \ 176 | LSDMR_CL3 \ 177 | LSDMR_RFEN \ 178 ) 179 180 /* 181 * The CADMUS registers are connected to CS3 on CDS. 182 * The new memory map places CADMUS at 0xf8000000. 183 * 184 * For BR3, need: 185 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 186 * port-size = 8-bits = BR[19:20] = 01 187 * no parity checking = BR[21:22] = 00 188 * GPMC for MSEL = BR[24:26] = 000 189 * Valid = BR[31] = 1 190 * 191 * 0 4 8 12 16 20 24 28 192 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 193 * 194 * For OR3, need: 195 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 196 * disable buffer ctrl OR[19] = 0 197 * CSNT OR[20] = 1 198 * ACS OR[21:22] = 11 199 * XACS OR[23] = 1 200 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 201 * SETA OR[28] = 0 202 * TRLX OR[29] = 1 203 * EHTR OR[30] = 1 204 * EAD extra time OR[31] = 1 205 * 206 * 0 4 8 12 16 20 24 28 207 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 208 */ 209 210 #define CONFIG_FSL_CADMUS 211 212 #define CADMUS_BASE_ADDR 0xf8000000 213 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 214 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 215 216 #define CONFIG_SYS_INIT_RAM_LOCK 1 217 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 218 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 219 220 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 221 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 222 223 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 224 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 225 226 /* Serial Port */ 227 #define CONFIG_SYS_NS16550_SERIAL 228 #define CONFIG_SYS_NS16550_REG_SIZE 1 229 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 230 231 #define CONFIG_SYS_BAUDRATE_TABLE \ 232 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 233 234 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 235 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 236 237 /* 238 * I2C 239 */ 240 #define CONFIG_SYS_I2C 241 #define CONFIG_SYS_I2C_FSL 242 #define CONFIG_SYS_FSL_I2C_SPEED 400000 243 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 244 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 245 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 246 247 /* EEPROM */ 248 #define CONFIG_ID_EEPROM 249 #define CONFIG_SYS_I2C_EEPROM_CCID 250 #define CONFIG_SYS_ID_EEPROM 251 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 252 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 253 254 /* 255 * General PCI 256 * Memory space is mapped 1-1, but I/O space must start from 0. 257 */ 258 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 259 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 260 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 261 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 262 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 263 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 264 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 265 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 266 267 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 268 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 269 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 270 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 271 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 272 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 273 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 274 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ 275 276 #ifdef CONFIG_LEGACY 277 #define BRIDGE_ID 17 278 #define VIA_ID 2 279 #else 280 #define BRIDGE_ID 28 281 #define VIA_ID 4 282 #endif 283 284 #if defined(CONFIG_PCI) 285 286 #define CONFIG_MPC85XX_PCI2 287 288 #undef CONFIG_EEPRO100 289 #undef CONFIG_TULIP 290 291 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 292 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 293 294 #endif /* CONFIG_PCI */ 295 296 #if defined(CONFIG_TSEC_ENET) 297 298 #define CONFIG_TSEC1 1 299 #define CONFIG_TSEC1_NAME "TSEC0" 300 #define CONFIG_TSEC2 1 301 #define CONFIG_TSEC2_NAME "TSEC1" 302 #define TSEC1_PHY_ADDR 0 303 #define TSEC2_PHY_ADDR 1 304 #define TSEC1_PHYIDX 0 305 #define TSEC2_PHYIDX 0 306 #define TSEC1_FLAGS TSEC_GIGABIT 307 #define TSEC2_FLAGS TSEC_GIGABIT 308 309 /* Options are: TSEC[0-1] */ 310 #define CONFIG_ETHPRIME "TSEC0" 311 312 #endif /* CONFIG_TSEC_ENET */ 313 314 /* 315 * Environment 316 */ 317 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 318 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 319 #define CONFIG_ENV_SIZE 0x2000 320 321 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 322 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 323 324 /* 325 * BOOTP options 326 */ 327 #define CONFIG_BOOTP_BOOTFILESIZE 328 329 #undef CONFIG_WATCHDOG /* watchdog disabled */ 330 331 /* 332 * Miscellaneous configurable options 333 */ 334 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 335 336 /* 337 * For booting Linux, the board info and command line data 338 * have to be in the first 64 MB of memory, since this is 339 * the maximum mapped by the Linux kernel during initialization. 340 */ 341 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 342 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 343 344 #if defined(CONFIG_CMD_KGDB) 345 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 346 #endif 347 348 /* 349 * Environment Configuration 350 */ 351 352 /* The mac addresses for all ethernet interface */ 353 #if defined(CONFIG_TSEC_ENET) 354 #define CONFIG_HAS_ETH0 355 #define CONFIG_HAS_ETH1 356 #define CONFIG_HAS_ETH2 357 #endif 358 359 #define CONFIG_IPADDR 192.168.1.253 360 361 #define CONFIG_HOSTNAME "unknown" 362 #define CONFIG_ROOTPATH "/nfsroot" 363 #define CONFIG_BOOTFILE "your.uImage" 364 365 #define CONFIG_SERVERIP 192.168.1.1 366 #define CONFIG_GATEWAYIP 192.168.1.1 367 #define CONFIG_NETMASK 255.255.255.0 368 369 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 370 371 #define CONFIG_EXTRA_ENV_SETTINGS \ 372 "netdev=eth0\0" \ 373 "consoledev=ttyS1\0" \ 374 "ramdiskaddr=600000\0" \ 375 "ramdiskfile=your.ramdisk.u-boot\0" \ 376 "fdtaddr=400000\0" \ 377 "fdtfile=your.fdt.dtb\0" 378 379 #define CONFIG_NFSBOOTCOMMAND \ 380 "setenv bootargs root=/dev/nfs rw " \ 381 "nfsroot=$serverip:$rootpath " \ 382 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 383 "console=$consoledev,$baudrate $othbootargs;" \ 384 "tftp $loadaddr $bootfile;" \ 385 "tftp $fdtaddr $fdtfile;" \ 386 "bootm $loadaddr - $fdtaddr" 387 388 #define CONFIG_RAMBOOTCOMMAND \ 389 "setenv bootargs root=/dev/ram rw " \ 390 "console=$consoledev,$baudrate $othbootargs;" \ 391 "tftp $ramdiskaddr $ramdiskfile;" \ 392 "tftp $loadaddr $bootfile;" \ 393 "bootm $loadaddr $ramdiskaddr" 394 395 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 396 397 #endif /* __CONFIG_H */ 398