1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8541cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 20 #define CONFIG_CPM2 1 /* has CPM2 */ 21 #define CONFIG_MPC8541 1 /* MPC8541 specific */ 22 #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ 23 24 #define CONFIG_SYS_TEXT_BASE 0xfff80000 25 26 #define CONFIG_PCI 27 #define CONFIG_PCI_INDIRECT_BRIDGE 28 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 29 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 30 #define CONFIG_ENV_OVERWRITE 31 32 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 33 34 #define CONFIG_FSL_VIA 35 36 #ifndef __ASSEMBLY__ 37 extern unsigned long get_clock_freq(void); 38 #endif 39 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 40 41 /* 42 * These can be toggled for performance analysis, otherwise use default. 43 */ 44 #define CONFIG_L2_CACHE /* toggle L2 cache */ 45 #define CONFIG_BTB /* toggle branch predition */ 46 47 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 48 #define CONFIG_SYS_MEMTEST_END 0x00400000 49 50 #define CONFIG_SYS_CCSRBAR 0xe0000000 51 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 52 53 /* DDR Setup */ 54 #define CONFIG_FSL_DDR1 55 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 56 #define CONFIG_DDR_SPD 57 #undef CONFIG_FSL_DDR_INTERACTIVE 58 59 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 60 61 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 62 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 63 64 #define CONFIG_NUM_DDR_CONTROLLERS 1 65 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 66 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 67 68 /* I2C addresses of SPD EEPROMs */ 69 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 70 71 /* 72 * Make sure required options are set 73 */ 74 #ifndef CONFIG_SPD_EEPROM 75 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 76 #endif 77 78 #undef CONFIG_CLOCKS_IN_MHZ 79 80 /* 81 * Local Bus Definitions 82 */ 83 84 /* 85 * FLASH on the Local Bus 86 * Two banks, 8M each, using the CFI driver. 87 * Boot from BR0/OR0 bank at 0xff00_0000 88 * Alternate BR1/OR1 bank at 0xff80_0000 89 * 90 * BR0, BR1: 91 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 92 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 93 * Port Size = 16 bits = BRx[19:20] = 10 94 * Use GPCM = BRx[24:26] = 000 95 * Valid = BRx[31] = 1 96 * 97 * 0 4 8 12 16 20 24 28 98 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 99 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 100 * 101 * OR0, OR1: 102 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 103 * Reserved ORx[17:18] = 11, confusion here? 104 * CSNT = ORx[20] = 1 105 * ACS = half cycle delay = ORx[21:22] = 11 106 * SCY = 6 = ORx[24:27] = 0110 107 * TRLX = use relaxed timing = ORx[29] = 1 108 * EAD = use external address latch delay = OR[31] = 1 109 * 110 * 0 4 8 12 16 20 24 28 111 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 112 */ 113 114 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 115 116 #define CONFIG_SYS_BR0_PRELIM 0xff801001 117 #define CONFIG_SYS_BR1_PRELIM 0xff001001 118 119 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 120 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 121 122 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 123 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 124 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 125 #undef CONFIG_SYS_FLASH_CHECKSUM 126 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 127 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 128 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 130 131 #define CONFIG_FLASH_CFI_DRIVER 132 #define CONFIG_SYS_FLASH_CFI 133 #define CONFIG_SYS_FLASH_EMPTY_INFO 134 135 136 /* 137 * SDRAM on the Local Bus 138 */ 139 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 140 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 141 142 /* 143 * Base Register 2 and Option Register 2 configure SDRAM. 144 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 145 * 146 * For BR2, need: 147 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 148 * port-size = 32-bits = BR2[19:20] = 11 149 * no parity checking = BR2[21:22] = 00 150 * SDRAM for MSEL = BR2[24:26] = 011 151 * Valid = BR[31] = 1 152 * 153 * 0 4 8 12 16 20 24 28 154 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 155 * 156 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 157 * FIXME: the top 17 bits of BR2. 158 */ 159 160 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 161 162 /* 163 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 164 * 165 * For OR2, need: 166 * 64MB mask for AM, OR2[0:7] = 1111 1100 167 * XAM, OR2[17:18] = 11 168 * 9 columns OR2[19-21] = 010 169 * 13 rows OR2[23-25] = 100 170 * EAD set for extra time OR[31] = 1 171 * 172 * 0 4 8 12 16 20 24 28 173 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 174 */ 175 176 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 177 178 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 179 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 180 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 181 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 182 183 /* 184 * Common settings for all Local Bus SDRAM commands. 185 * At run time, either BSMA1516 (for CPU 1.1) 186 * or BSMA1617 (for CPU 1.0) (old) 187 * is OR'ed in too. 188 */ 189 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 190 | LSDMR_PRETOACT7 \ 191 | LSDMR_ACTTORW7 \ 192 | LSDMR_BL8 \ 193 | LSDMR_WRC4 \ 194 | LSDMR_CL3 \ 195 | LSDMR_RFEN \ 196 ) 197 198 /* 199 * The CADMUS registers are connected to CS3 on CDS. 200 * The new memory map places CADMUS at 0xf8000000. 201 * 202 * For BR3, need: 203 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 204 * port-size = 8-bits = BR[19:20] = 01 205 * no parity checking = BR[21:22] = 00 206 * GPMC for MSEL = BR[24:26] = 000 207 * Valid = BR[31] = 1 208 * 209 * 0 4 8 12 16 20 24 28 210 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 211 * 212 * For OR3, need: 213 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 214 * disable buffer ctrl OR[19] = 0 215 * CSNT OR[20] = 1 216 * ACS OR[21:22] = 11 217 * XACS OR[23] = 1 218 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 219 * SETA OR[28] = 0 220 * TRLX OR[29] = 1 221 * EHTR OR[30] = 1 222 * EAD extra time OR[31] = 1 223 * 224 * 0 4 8 12 16 20 24 28 225 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 226 */ 227 228 #define CONFIG_FSL_CADMUS 229 230 #define CADMUS_BASE_ADDR 0xf8000000 231 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 232 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 233 234 #define CONFIG_SYS_INIT_RAM_LOCK 1 235 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 236 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 237 238 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 239 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 240 241 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 242 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 243 244 /* Serial Port */ 245 #define CONFIG_CONS_INDEX 2 246 #define CONFIG_SYS_NS16550 247 #define CONFIG_SYS_NS16550_SERIAL 248 #define CONFIG_SYS_NS16550_REG_SIZE 1 249 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 250 251 #define CONFIG_SYS_BAUDRATE_TABLE \ 252 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 253 254 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 255 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 256 257 /* Use the HUSH parser */ 258 #define CONFIG_SYS_HUSH_PARSER 259 #ifdef CONFIG_SYS_HUSH_PARSER 260 #endif 261 262 /* pass open firmware flat tree */ 263 #define CONFIG_OF_LIBFDT 1 264 #define CONFIG_OF_BOARD_SETUP 1 265 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 266 267 /* 268 * I2C 269 */ 270 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 271 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 272 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 273 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 274 #define CONFIG_SYS_I2C_SLAVE 0x7F 275 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 276 #define CONFIG_SYS_I2C_OFFSET 0x3000 277 278 /* EEPROM */ 279 #define CONFIG_ID_EEPROM 280 #define CONFIG_SYS_I2C_EEPROM_CCID 281 #define CONFIG_SYS_ID_EEPROM 282 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 283 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 284 285 /* 286 * General PCI 287 * Memory space is mapped 1-1, but I/O space must start from 0. 288 */ 289 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 290 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 291 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 292 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 293 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 294 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 295 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 296 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 297 298 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 299 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 300 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 301 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 302 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 303 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 304 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 305 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ 306 307 #ifdef CONFIG_LEGACY 308 #define BRIDGE_ID 17 309 #define VIA_ID 2 310 #else 311 #define BRIDGE_ID 28 312 #define VIA_ID 4 313 #endif 314 315 #if defined(CONFIG_PCI) 316 317 #define CONFIG_MPC85XX_PCI2 318 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 319 320 #undef CONFIG_EEPRO100 321 #undef CONFIG_TULIP 322 323 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 324 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 325 326 #endif /* CONFIG_PCI */ 327 328 329 #if defined(CONFIG_TSEC_ENET) 330 331 #define CONFIG_MII 1 /* MII PHY management */ 332 #define CONFIG_TSEC1 1 333 #define CONFIG_TSEC1_NAME "TSEC0" 334 #define CONFIG_TSEC2 1 335 #define CONFIG_TSEC2_NAME "TSEC1" 336 #define TSEC1_PHY_ADDR 0 337 #define TSEC2_PHY_ADDR 1 338 #define TSEC1_PHYIDX 0 339 #define TSEC2_PHYIDX 0 340 #define TSEC1_FLAGS TSEC_GIGABIT 341 #define TSEC2_FLAGS TSEC_GIGABIT 342 343 /* Options are: TSEC[0-1] */ 344 #define CONFIG_ETHPRIME "TSEC0" 345 346 #endif /* CONFIG_TSEC_ENET */ 347 348 /* 349 * Environment 350 */ 351 #define CONFIG_ENV_IS_IN_FLASH 1 352 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 353 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 354 #define CONFIG_ENV_SIZE 0x2000 355 356 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 357 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 358 359 /* 360 * BOOTP options 361 */ 362 #define CONFIG_BOOTP_BOOTFILESIZE 363 #define CONFIG_BOOTP_BOOTPATH 364 #define CONFIG_BOOTP_GATEWAY 365 #define CONFIG_BOOTP_HOSTNAME 366 367 368 /* 369 * Command line configuration. 370 */ 371 #include <config_cmd_default.h> 372 373 #define CONFIG_CMD_PING 374 #define CONFIG_CMD_I2C 375 #define CONFIG_CMD_MII 376 #define CONFIG_CMD_ELF 377 #define CONFIG_CMD_IRQ 378 #define CONFIG_CMD_SETEXPR 379 #define CONFIG_CMD_REGINFO 380 381 #if defined(CONFIG_PCI) 382 #define CONFIG_CMD_PCI 383 #endif 384 385 386 #undef CONFIG_WATCHDOG /* watchdog disabled */ 387 388 /* 389 * Miscellaneous configurable options 390 */ 391 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 392 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 393 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 394 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 395 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 396 #if defined(CONFIG_CMD_KGDB) 397 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 398 #else 399 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 400 #endif 401 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 402 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 403 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 404 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 405 406 /* 407 * For booting Linux, the board info and command line data 408 * have to be in the first 64 MB of memory, since this is 409 * the maximum mapped by the Linux kernel during initialization. 410 */ 411 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 412 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 413 414 #if defined(CONFIG_CMD_KGDB) 415 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 416 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 417 #endif 418 419 /* 420 * Environment Configuration 421 */ 422 423 /* The mac addresses for all ethernet interface */ 424 #if defined(CONFIG_TSEC_ENET) 425 #define CONFIG_HAS_ETH0 426 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 427 #define CONFIG_HAS_ETH1 428 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 429 #define CONFIG_HAS_ETH2 430 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 431 #endif 432 433 #define CONFIG_IPADDR 192.168.1.253 434 435 #define CONFIG_HOSTNAME unknown 436 #define CONFIG_ROOTPATH "/nfsroot" 437 #define CONFIG_BOOTFILE "your.uImage" 438 439 #define CONFIG_SERVERIP 192.168.1.1 440 #define CONFIG_GATEWAYIP 192.168.1.1 441 #define CONFIG_NETMASK 255.255.255.0 442 443 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 444 445 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 446 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 447 448 #define CONFIG_BAUDRATE 115200 449 450 #define CONFIG_EXTRA_ENV_SETTINGS \ 451 "netdev=eth0\0" \ 452 "consoledev=ttyS1\0" \ 453 "ramdiskaddr=600000\0" \ 454 "ramdiskfile=your.ramdisk.u-boot\0" \ 455 "fdtaddr=400000\0" \ 456 "fdtfile=your.fdt.dtb\0" 457 458 #define CONFIG_NFSBOOTCOMMAND \ 459 "setenv bootargs root=/dev/nfs rw " \ 460 "nfsroot=$serverip:$rootpath " \ 461 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 462 "console=$consoledev,$baudrate $othbootargs;" \ 463 "tftp $loadaddr $bootfile;" \ 464 "tftp $fdtaddr $fdtfile;" \ 465 "bootm $loadaddr - $fdtaddr" 466 467 #define CONFIG_RAMBOOTCOMMAND \ 468 "setenv bootargs root=/dev/ram rw " \ 469 "console=$consoledev,$baudrate $othbootargs;" \ 470 "tftp $ramdiskaddr $ramdiskfile;" \ 471 "tftp $loadaddr $bootfile;" \ 472 "bootm $loadaddr $ramdiskaddr" 473 474 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 475 476 #endif /* __CONFIG_H */ 477