1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8541cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 36 #define CONFIG_CPM2 1 /* has CPM2 */ 37 #define CONFIG_MPC8541 1 /* MPC8541 specific */ 38 #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ 39 40 #define CONFIG_PCI 41 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 42 #define CONFIG_ENV_OVERWRITE 43 44 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 45 46 #define CONFIG_FSL_VIA 47 48 /* 49 * When initializing flash, if we cannot find the manufacturer ID, 50 * assume this is the AMD flash associated with the CDS board. 51 * This allows booting from a promjet. 52 */ 53 #define CONFIG_ASSUME_AMD_FLASH 54 55 #ifndef __ASSEMBLY__ 56 extern unsigned long get_clock_freq(void); 57 #endif 58 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 59 60 /* 61 * These can be toggled for performance analysis, otherwise use default. 62 */ 63 #define CONFIG_L2_CACHE /* toggle L2 cache */ 64 #define CONFIG_BTB /* toggle branch predition */ 65 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 66 67 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 68 #define CFG_MEMTEST_END 0x00400000 69 70 /* 71 * Base addresses -- Note these are effective addresses where the 72 * actual resources get mapped (not physical addresses) 73 */ 74 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 75 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 76 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 77 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 78 79 /* DDR Setup */ 80 #define CONFIG_FSL_DDR1 81 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 82 #define CONFIG_DDR_SPD 83 #undef CONFIG_FSL_DDR_INTERACTIVE 84 85 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 86 87 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 88 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 89 90 #define CONFIG_NUM_DDR_CONTROLLERS 1 91 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 92 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 93 94 /* I2C addresses of SPD EEPROMs */ 95 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 96 97 /* 98 * Make sure required options are set 99 */ 100 #ifndef CONFIG_SPD_EEPROM 101 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 102 #endif 103 104 #undef CONFIG_CLOCKS_IN_MHZ 105 106 /* 107 * Local Bus Definitions 108 */ 109 110 /* 111 * FLASH on the Local Bus 112 * Two banks, 8M each, using the CFI driver. 113 * Boot from BR0/OR0 bank at 0xff00_0000 114 * Alternate BR1/OR1 bank at 0xff80_0000 115 * 116 * BR0, BR1: 117 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 118 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 119 * Port Size = 16 bits = BRx[19:20] = 10 120 * Use GPCM = BRx[24:26] = 000 121 * Valid = BRx[31] = 1 122 * 123 * 0 4 8 12 16 20 24 28 124 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 125 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 126 * 127 * OR0, OR1: 128 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 129 * Reserved ORx[17:18] = 11, confusion here? 130 * CSNT = ORx[20] = 1 131 * ACS = half cycle delay = ORx[21:22] = 11 132 * SCY = 6 = ORx[24:27] = 0110 133 * TRLX = use relaxed timing = ORx[29] = 1 134 * EAD = use external address latch delay = OR[31] = 1 135 * 136 * 0 4 8 12 16 20 24 28 137 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 138 */ 139 140 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 141 142 #define CFG_BR0_PRELIM 0xff801001 143 #define CFG_BR1_PRELIM 0xff001001 144 145 #define CFG_OR0_PRELIM 0xff806e65 146 #define CFG_OR1_PRELIM 0xff806e65 147 148 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} 149 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 150 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 151 #undef CFG_FLASH_CHECKSUM 152 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 153 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 154 155 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 156 157 #define CONFIG_FLASH_CFI_DRIVER 158 #define CFG_FLASH_CFI 159 #define CFG_FLASH_EMPTY_INFO 160 161 162 /* 163 * SDRAM on the Local Bus 164 */ 165 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 166 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 167 168 /* 169 * Base Register 2 and Option Register 2 configure SDRAM. 170 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 171 * 172 * For BR2, need: 173 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 174 * port-size = 32-bits = BR2[19:20] = 11 175 * no parity checking = BR2[21:22] = 00 176 * SDRAM for MSEL = BR2[24:26] = 011 177 * Valid = BR[31] = 1 178 * 179 * 0 4 8 12 16 20 24 28 180 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 181 * 182 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 183 * FIXME: the top 17 bits of BR2. 184 */ 185 186 #define CFG_BR2_PRELIM 0xf0001861 187 188 /* 189 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 190 * 191 * For OR2, need: 192 * 64MB mask for AM, OR2[0:7] = 1111 1100 193 * XAM, OR2[17:18] = 11 194 * 9 columns OR2[19-21] = 010 195 * 13 rows OR2[23-25] = 100 196 * EAD set for extra time OR[31] = 1 197 * 198 * 0 4 8 12 16 20 24 28 199 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 200 */ 201 202 #define CFG_OR2_PRELIM 0xfc006901 203 204 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 205 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 206 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 207 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 208 209 /* 210 * LSDMR masks 211 */ 212 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 213 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 214 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 215 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 216 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 217 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 218 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 219 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 220 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 221 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 222 223 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 224 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 225 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 230 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 231 232 /* 233 * Common settings for all Local Bus SDRAM commands. 234 * At run time, either BSMA1516 (for CPU 1.1) 235 * or BSMA1617 (for CPU 1.0) (old) 236 * is OR'ed in too. 237 */ 238 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 239 | CFG_LBC_LSDMR_PRETOACT7 \ 240 | CFG_LBC_LSDMR_ACTTORW7 \ 241 | CFG_LBC_LSDMR_BL8 \ 242 | CFG_LBC_LSDMR_WRC4 \ 243 | CFG_LBC_LSDMR_CL3 \ 244 | CFG_LBC_LSDMR_RFEN \ 245 ) 246 247 /* 248 * The CADMUS registers are connected to CS3 on CDS. 249 * The new memory map places CADMUS at 0xf8000000. 250 * 251 * For BR3, need: 252 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 253 * port-size = 8-bits = BR[19:20] = 01 254 * no parity checking = BR[21:22] = 00 255 * GPMC for MSEL = BR[24:26] = 000 256 * Valid = BR[31] = 1 257 * 258 * 0 4 8 12 16 20 24 28 259 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 260 * 261 * For OR3, need: 262 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 263 * disable buffer ctrl OR[19] = 0 264 * CSNT OR[20] = 1 265 * ACS OR[21:22] = 11 266 * XACS OR[23] = 1 267 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 268 * SETA OR[28] = 0 269 * TRLX OR[29] = 1 270 * EHTR OR[30] = 1 271 * EAD extra time OR[31] = 1 272 * 273 * 0 4 8 12 16 20 24 28 274 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 275 */ 276 277 #define CONFIG_FSL_CADMUS 278 279 #define CADMUS_BASE_ADDR 0xf8000000 280 #define CFG_BR3_PRELIM 0xf8000801 281 #define CFG_OR3_PRELIM 0xfff00ff7 282 283 #define CONFIG_L1_INIT_RAM 284 #define CFG_INIT_RAM_LOCK 1 285 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 286 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 287 288 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 289 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 290 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 291 292 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 293 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 294 295 /* Serial Port */ 296 #define CONFIG_CONS_INDEX 2 297 #undef CONFIG_SERIAL_SOFTWARE_FIFO 298 #define CFG_NS16550 299 #define CFG_NS16550_SERIAL 300 #define CFG_NS16550_REG_SIZE 1 301 #define CFG_NS16550_CLK get_bus_freq(0) 302 303 #define CFG_BAUDRATE_TABLE \ 304 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 305 306 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 307 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 308 309 /* Use the HUSH parser */ 310 #define CFG_HUSH_PARSER 311 #ifdef CFG_HUSH_PARSER 312 #define CFG_PROMPT_HUSH_PS2 "> " 313 #endif 314 315 /* pass open firmware flat tree */ 316 #define CONFIG_OF_LIBFDT 1 317 #define CONFIG_OF_BOARD_SETUP 1 318 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 319 320 #define CFG_64BIT_VSPRINTF 1 321 #define CFG_64BIT_STRTOUL 1 322 323 /* 324 * I2C 325 */ 326 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 327 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 328 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 329 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 330 #define CFG_I2C_SLAVE 0x7F 331 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 332 #define CFG_I2C_OFFSET 0x3000 333 334 /* EEPROM */ 335 #define CONFIG_ID_EEPROM 336 #define CFG_I2C_EEPROM_CCID 337 #define CFG_ID_EEPROM 338 #define CFG_I2C_EEPROM_ADDR 0x57 339 #define CFG_I2C_EEPROM_ADDR_LEN 2 340 341 /* 342 * General PCI 343 * Memory space is mapped 1-1, but I/O space must start from 0. 344 */ 345 #define CFG_PCI1_MEM_BASE 0x80000000 346 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 347 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 348 #define CFG_PCI1_IO_BASE 0x00000000 349 #define CFG_PCI1_IO_PHYS 0xe2000000 350 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ 351 352 #define CFG_PCI2_MEM_BASE 0xa0000000 353 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 354 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 355 #define CFG_PCI2_IO_BASE 0x00000000 356 #define CFG_PCI2_IO_PHYS 0xe2100000 357 #define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ 358 359 #ifdef CONFIG_LEGACY 360 #define BRIDGE_ID 17 361 #define VIA_ID 2 362 #else 363 #define BRIDGE_ID 28 364 #define VIA_ID 4 365 #endif 366 367 #if defined(CONFIG_PCI) 368 369 #define CONFIG_MPC85XX_PCI2 370 #define CONFIG_NET_MULTI 371 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 372 373 #undef CONFIG_EEPRO100 374 #undef CONFIG_TULIP 375 376 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 377 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 378 379 #endif /* CONFIG_PCI */ 380 381 382 #if defined(CONFIG_TSEC_ENET) 383 384 #ifndef CONFIG_NET_MULTI 385 #define CONFIG_NET_MULTI 1 386 #endif 387 388 #define CONFIG_MII 1 /* MII PHY management */ 389 #define CONFIG_TSEC1 1 390 #define CONFIG_TSEC1_NAME "TSEC0" 391 #define CONFIG_TSEC2 1 392 #define CONFIG_TSEC2_NAME "TSEC1" 393 #define TSEC1_PHY_ADDR 0 394 #define TSEC2_PHY_ADDR 1 395 #define TSEC1_PHYIDX 0 396 #define TSEC2_PHYIDX 0 397 #define TSEC1_FLAGS TSEC_GIGABIT 398 #define TSEC2_FLAGS TSEC_GIGABIT 399 400 /* Options are: TSEC[0-1] */ 401 #define CONFIG_ETHPRIME "TSEC0" 402 403 #endif /* CONFIG_TSEC_ENET */ 404 405 /* 406 * Environment 407 */ 408 #define CFG_ENV_IS_IN_FLASH 1 409 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 410 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 411 #define CFG_ENV_SIZE 0x2000 412 413 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 414 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 415 416 /* 417 * BOOTP options 418 */ 419 #define CONFIG_BOOTP_BOOTFILESIZE 420 #define CONFIG_BOOTP_BOOTPATH 421 #define CONFIG_BOOTP_GATEWAY 422 #define CONFIG_BOOTP_HOSTNAME 423 424 425 /* 426 * Command line configuration. 427 */ 428 #include <config_cmd_default.h> 429 430 #define CONFIG_CMD_PING 431 #define CONFIG_CMD_I2C 432 #define CONFIG_CMD_MII 433 #define CONFIG_CMD_ELF 434 435 #if defined(CONFIG_PCI) 436 #define CONFIG_CMD_PCI 437 #endif 438 439 440 #undef CONFIG_WATCHDOG /* watchdog disabled */ 441 442 /* 443 * Miscellaneous configurable options 444 */ 445 #define CFG_LONGHELP /* undef to save memory */ 446 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 447 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 448 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 449 #if defined(CONFIG_CMD_KGDB) 450 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 451 #else 452 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 453 #endif 454 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 455 #define CFG_MAXARGS 16 /* max number of command args */ 456 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 457 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 458 459 /* 460 * For booting Linux, the board info and command line data 461 * have to be in the first 8 MB of memory, since this is 462 * the maximum mapped by the Linux kernel during initialization. 463 */ 464 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 465 466 /* 467 * Internal Definitions 468 * 469 * Boot Flags 470 */ 471 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 472 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 473 474 #if defined(CONFIG_CMD_KGDB) 475 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 476 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 477 #endif 478 479 /* 480 * Environment Configuration 481 */ 482 483 /* The mac addresses for all ethernet interface */ 484 #if defined(CONFIG_TSEC_ENET) 485 #define CONFIG_HAS_ETH0 486 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 487 #define CONFIG_HAS_ETH1 488 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 489 #define CONFIG_HAS_ETH2 490 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 491 #endif 492 493 #define CONFIG_IPADDR 192.168.1.253 494 495 #define CONFIG_HOSTNAME unknown 496 #define CONFIG_ROOTPATH /nfsroot 497 #define CONFIG_BOOTFILE your.uImage 498 499 #define CONFIG_SERVERIP 192.168.1.1 500 #define CONFIG_GATEWAYIP 192.168.1.1 501 #define CONFIG_NETMASK 255.255.255.0 502 503 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 504 505 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 506 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 507 508 #define CONFIG_BAUDRATE 115200 509 510 #define CONFIG_EXTRA_ENV_SETTINGS \ 511 "netdev=eth0\0" \ 512 "consoledev=ttyS1\0" \ 513 "ramdiskaddr=600000\0" \ 514 "ramdiskfile=your.ramdisk.u-boot\0" \ 515 "fdtaddr=400000\0" \ 516 "fdtfile=your.fdt.dtb\0" 517 518 #define CONFIG_NFSBOOTCOMMAND \ 519 "setenv bootargs root=/dev/nfs rw " \ 520 "nfsroot=$serverip:$rootpath " \ 521 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 522 "console=$consoledev,$baudrate $othbootargs;" \ 523 "tftp $loadaddr $bootfile;" \ 524 "tftp $fdtaddr $fdtfile;" \ 525 "bootm $loadaddr - $fdtaddr" 526 527 #define CONFIG_RAMBOOTCOMMAND \ 528 "setenv bootargs root=/dev/ram rw " \ 529 "console=$consoledev,$baudrate $othbootargs;" \ 530 "tftp $ramdiskaddr $ramdiskfile;" \ 531 "tftp $loadaddr $bootfile;" \ 532 "bootm $loadaddr $ramdiskaddr" 533 534 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 535 536 #endif /* __CONFIG_H */ 537