1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8541cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_CPM2 1 /* has CPM2 */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xfff80000 22 23 #define CONFIG_PCI_INDIRECT_BRIDGE 24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 25 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 26 #define CONFIG_ENV_OVERWRITE 27 28 #define CONFIG_FSL_VIA 29 30 #ifndef __ASSEMBLY__ 31 extern unsigned long get_clock_freq(void); 32 #endif 33 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 34 35 /* 36 * These can be toggled for performance analysis, otherwise use default. 37 */ 38 #define CONFIG_L2_CACHE /* toggle L2 cache */ 39 #define CONFIG_BTB /* toggle branch predition */ 40 41 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 42 #define CONFIG_SYS_MEMTEST_END 0x00400000 43 44 #define CONFIG_SYS_CCSRBAR 0xe0000000 45 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 46 47 /* DDR Setup */ 48 #define CONFIG_SYS_FSL_DDR1 49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 50 #define CONFIG_DDR_SPD 51 #undef CONFIG_FSL_DDR_INTERACTIVE 52 53 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 54 55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 57 58 #define CONFIG_NUM_DDR_CONTROLLERS 1 59 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 60 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 61 62 /* I2C addresses of SPD EEPROMs */ 63 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 64 65 /* 66 * Make sure required options are set 67 */ 68 #ifndef CONFIG_SPD_EEPROM 69 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 70 #endif 71 72 #undef CONFIG_CLOCKS_IN_MHZ 73 74 /* 75 * Local Bus Definitions 76 */ 77 78 /* 79 * FLASH on the Local Bus 80 * Two banks, 8M each, using the CFI driver. 81 * Boot from BR0/OR0 bank at 0xff00_0000 82 * Alternate BR1/OR1 bank at 0xff80_0000 83 * 84 * BR0, BR1: 85 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 86 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 87 * Port Size = 16 bits = BRx[19:20] = 10 88 * Use GPCM = BRx[24:26] = 000 89 * Valid = BRx[31] = 1 90 * 91 * 0 4 8 12 16 20 24 28 92 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 93 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 94 * 95 * OR0, OR1: 96 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 97 * Reserved ORx[17:18] = 11, confusion here? 98 * CSNT = ORx[20] = 1 99 * ACS = half cycle delay = ORx[21:22] = 11 100 * SCY = 6 = ORx[24:27] = 0110 101 * TRLX = use relaxed timing = ORx[29] = 1 102 * EAD = use external address latch delay = OR[31] = 1 103 * 104 * 0 4 8 12 16 20 24 28 105 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 106 */ 107 108 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 109 110 #define CONFIG_SYS_BR0_PRELIM 0xff801001 111 #define CONFIG_SYS_BR1_PRELIM 0xff001001 112 113 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 114 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 115 116 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 117 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 118 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 119 #undef CONFIG_SYS_FLASH_CHECKSUM 120 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 121 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 122 123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 124 125 #define CONFIG_FLASH_CFI_DRIVER 126 #define CONFIG_SYS_FLASH_CFI 127 #define CONFIG_SYS_FLASH_EMPTY_INFO 128 129 /* 130 * SDRAM on the Local Bus 131 */ 132 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 133 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 134 135 /* 136 * Base Register 2 and Option Register 2 configure SDRAM. 137 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 138 * 139 * For BR2, need: 140 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 141 * port-size = 32-bits = BR2[19:20] = 11 142 * no parity checking = BR2[21:22] = 00 143 * SDRAM for MSEL = BR2[24:26] = 011 144 * Valid = BR[31] = 1 145 * 146 * 0 4 8 12 16 20 24 28 147 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 148 * 149 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 150 * FIXME: the top 17 bits of BR2. 151 */ 152 153 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 154 155 /* 156 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 157 * 158 * For OR2, need: 159 * 64MB mask for AM, OR2[0:7] = 1111 1100 160 * XAM, OR2[17:18] = 11 161 * 9 columns OR2[19-21] = 010 162 * 13 rows OR2[23-25] = 100 163 * EAD set for extra time OR[31] = 1 164 * 165 * 0 4 8 12 16 20 24 28 166 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 167 */ 168 169 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 170 171 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 172 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 173 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 174 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 175 176 /* 177 * Common settings for all Local Bus SDRAM commands. 178 * At run time, either BSMA1516 (for CPU 1.1) 179 * or BSMA1617 (for CPU 1.0) (old) 180 * is OR'ed in too. 181 */ 182 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 183 | LSDMR_PRETOACT7 \ 184 | LSDMR_ACTTORW7 \ 185 | LSDMR_BL8 \ 186 | LSDMR_WRC4 \ 187 | LSDMR_CL3 \ 188 | LSDMR_RFEN \ 189 ) 190 191 /* 192 * The CADMUS registers are connected to CS3 on CDS. 193 * The new memory map places CADMUS at 0xf8000000. 194 * 195 * For BR3, need: 196 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 197 * port-size = 8-bits = BR[19:20] = 01 198 * no parity checking = BR[21:22] = 00 199 * GPMC for MSEL = BR[24:26] = 000 200 * Valid = BR[31] = 1 201 * 202 * 0 4 8 12 16 20 24 28 203 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 204 * 205 * For OR3, need: 206 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 207 * disable buffer ctrl OR[19] = 0 208 * CSNT OR[20] = 1 209 * ACS OR[21:22] = 11 210 * XACS OR[23] = 1 211 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 212 * SETA OR[28] = 0 213 * TRLX OR[29] = 1 214 * EHTR OR[30] = 1 215 * EAD extra time OR[31] = 1 216 * 217 * 0 4 8 12 16 20 24 28 218 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 219 */ 220 221 #define CONFIG_FSL_CADMUS 222 223 #define CADMUS_BASE_ADDR 0xf8000000 224 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 225 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 226 227 #define CONFIG_SYS_INIT_RAM_LOCK 1 228 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 229 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 230 231 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 232 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 233 234 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 235 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 236 237 /* Serial Port */ 238 #define CONFIG_CONS_INDEX 2 239 #define CONFIG_SYS_NS16550_SERIAL 240 #define CONFIG_SYS_NS16550_REG_SIZE 1 241 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 242 243 #define CONFIG_SYS_BAUDRATE_TABLE \ 244 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 245 246 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 247 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 248 249 /* 250 * I2C 251 */ 252 #define CONFIG_SYS_I2C 253 #define CONFIG_SYS_I2C_FSL 254 #define CONFIG_SYS_FSL_I2C_SPEED 400000 255 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 256 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 257 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 258 259 /* EEPROM */ 260 #define CONFIG_ID_EEPROM 261 #define CONFIG_SYS_I2C_EEPROM_CCID 262 #define CONFIG_SYS_ID_EEPROM 263 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 264 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 265 266 /* 267 * General PCI 268 * Memory space is mapped 1-1, but I/O space must start from 0. 269 */ 270 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 271 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 272 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 273 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 274 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 275 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 276 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 277 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 278 279 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 280 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 281 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 282 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 283 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 284 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 285 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 286 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ 287 288 #ifdef CONFIG_LEGACY 289 #define BRIDGE_ID 17 290 #define VIA_ID 2 291 #else 292 #define BRIDGE_ID 28 293 #define VIA_ID 4 294 #endif 295 296 #if defined(CONFIG_PCI) 297 298 #define CONFIG_MPC85XX_PCI2 299 300 #undef CONFIG_EEPRO100 301 #undef CONFIG_TULIP 302 303 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 304 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 305 306 #endif /* CONFIG_PCI */ 307 308 #if defined(CONFIG_TSEC_ENET) 309 310 #define CONFIG_MII 1 /* MII PHY management */ 311 #define CONFIG_TSEC1 1 312 #define CONFIG_TSEC1_NAME "TSEC0" 313 #define CONFIG_TSEC2 1 314 #define CONFIG_TSEC2_NAME "TSEC1" 315 #define TSEC1_PHY_ADDR 0 316 #define TSEC2_PHY_ADDR 1 317 #define TSEC1_PHYIDX 0 318 #define TSEC2_PHYIDX 0 319 #define TSEC1_FLAGS TSEC_GIGABIT 320 #define TSEC2_FLAGS TSEC_GIGABIT 321 322 /* Options are: TSEC[0-1] */ 323 #define CONFIG_ETHPRIME "TSEC0" 324 325 #endif /* CONFIG_TSEC_ENET */ 326 327 /* 328 * Environment 329 */ 330 #define CONFIG_ENV_IS_IN_FLASH 1 331 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 332 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 333 #define CONFIG_ENV_SIZE 0x2000 334 335 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 336 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 337 338 /* 339 * BOOTP options 340 */ 341 #define CONFIG_BOOTP_BOOTFILESIZE 342 #define CONFIG_BOOTP_BOOTPATH 343 #define CONFIG_BOOTP_GATEWAY 344 #define CONFIG_BOOTP_HOSTNAME 345 346 /* 347 * Command line configuration. 348 */ 349 #define CONFIG_CMD_IRQ 350 #define CONFIG_CMD_REGINFO 351 352 #if defined(CONFIG_PCI) 353 #define CONFIG_CMD_PCI 354 #endif 355 356 #undef CONFIG_WATCHDOG /* watchdog disabled */ 357 358 /* 359 * Miscellaneous configurable options 360 */ 361 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 362 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 363 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 364 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 365 #if defined(CONFIG_CMD_KGDB) 366 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 367 #else 368 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 369 #endif 370 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 371 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 372 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 373 374 /* 375 * For booting Linux, the board info and command line data 376 * have to be in the first 64 MB of memory, since this is 377 * the maximum mapped by the Linux kernel during initialization. 378 */ 379 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 380 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 381 382 #if defined(CONFIG_CMD_KGDB) 383 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 384 #endif 385 386 /* 387 * Environment Configuration 388 */ 389 390 /* The mac addresses for all ethernet interface */ 391 #if defined(CONFIG_TSEC_ENET) 392 #define CONFIG_HAS_ETH0 393 #define CONFIG_HAS_ETH1 394 #define CONFIG_HAS_ETH2 395 #endif 396 397 #define CONFIG_IPADDR 192.168.1.253 398 399 #define CONFIG_HOSTNAME unknown 400 #define CONFIG_ROOTPATH "/nfsroot" 401 #define CONFIG_BOOTFILE "your.uImage" 402 403 #define CONFIG_SERVERIP 192.168.1.1 404 #define CONFIG_GATEWAYIP 192.168.1.1 405 #define CONFIG_NETMASK 255.255.255.0 406 407 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 408 409 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 410 411 #define CONFIG_BAUDRATE 115200 412 413 #define CONFIG_EXTRA_ENV_SETTINGS \ 414 "netdev=eth0\0" \ 415 "consoledev=ttyS1\0" \ 416 "ramdiskaddr=600000\0" \ 417 "ramdiskfile=your.ramdisk.u-boot\0" \ 418 "fdtaddr=400000\0" \ 419 "fdtfile=your.fdt.dtb\0" 420 421 #define CONFIG_NFSBOOTCOMMAND \ 422 "setenv bootargs root=/dev/nfs rw " \ 423 "nfsroot=$serverip:$rootpath " \ 424 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 425 "console=$consoledev,$baudrate $othbootargs;" \ 426 "tftp $loadaddr $bootfile;" \ 427 "tftp $fdtaddr $fdtfile;" \ 428 "bootm $loadaddr - $fdtaddr" 429 430 #define CONFIG_RAMBOOTCOMMAND \ 431 "setenv bootargs root=/dev/ram rw " \ 432 "console=$consoledev,$baudrate $othbootargs;" \ 433 "tftp $ramdiskaddr $ramdiskfile;" \ 434 "tftp $loadaddr $bootfile;" \ 435 "bootm $loadaddr $ramdiskaddr" 436 437 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 438 439 #endif /* __CONFIG_H */ 440