1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8540ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 1 /* BOOKE */ 23 #define CONFIG_E500 1 /* BOOKE e500 family */ 24 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 25 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 26 27 /* 28 * default CCARBAR is at 0xff700000 29 * assume U-Boot is less than 0.5MB 30 */ 31 #define CONFIG_SYS_TEXT_BASE 0xfff80000 32 33 #ifndef CONFIG_HAS_FEC 34 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 35 #endif 36 37 #define CONFIG_PCI 38 #define CONFIG_PCI_INDIRECT_BRIDGE 39 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 40 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 41 #define CONFIG_ENV_OVERWRITE 42 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 43 44 /* 45 * sysclk for MPC85xx 46 * 47 * Two valid values are: 48 * 33000000 49 * 66000000 50 * 51 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 52 * is likely the desired value here, so that is now the default. 53 * The board, however, can run at 66MHz. In any event, this value 54 * must match the settings of some switches. Details can be found 55 * in the README.mpc85xxads. 56 * 57 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 58 * 33MHz to accommodate, based on a PCI pin. 59 * Note that PCI-X won't work at 33MHz. 60 */ 61 62 #ifndef CONFIG_SYS_CLK_FREQ 63 #define CONFIG_SYS_CLK_FREQ 33000000 64 #endif 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 72 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 73 #define CONFIG_SYS_MEMTEST_END 0x00400000 74 75 #define CONFIG_SYS_CCSRBAR 0xe0000000 76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 77 78 /* DDR Setup */ 79 #define CONFIG_SYS_FSL_DDR1 80 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 81 #define CONFIG_DDR_SPD 82 #undef CONFIG_FSL_DDR_INTERACTIVE 83 84 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 85 86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 88 89 #define CONFIG_NUM_DDR_CONTROLLERS 1 90 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 91 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 92 93 /* I2C addresses of SPD EEPROMs */ 94 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 95 96 /* These are used when DDR doesn't use SPD. */ 97 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 98 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 99 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 100 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 101 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 102 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 103 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 104 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 105 106 /* 107 * SDRAM on the Local Bus 108 */ 109 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 110 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 111 112 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 113 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 114 115 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 116 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 117 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 118 #undef CONFIG_SYS_FLASH_CHECKSUM 119 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 120 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 121 122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 123 124 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 125 #define CONFIG_SYS_RAMBOOT 126 #else 127 #undef CONFIG_SYS_RAMBOOT 128 #endif 129 130 #define CONFIG_FLASH_CFI_DRIVER 131 #define CONFIG_SYS_FLASH_CFI 132 #define CONFIG_SYS_FLASH_EMPTY_INFO 133 134 #undef CONFIG_CLOCKS_IN_MHZ 135 136 /* 137 * Local Bus Definitions 138 */ 139 140 /* 141 * Base Register 2 and Option Register 2 configure SDRAM. 142 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 143 * 144 * For BR2, need: 145 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 146 * port-size = 32-bits = BR2[19:20] = 11 147 * no parity checking = BR2[21:22] = 00 148 * SDRAM for MSEL = BR2[24:26] = 011 149 * Valid = BR[31] = 1 150 * 151 * 0 4 8 12 16 20 24 28 152 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 153 * 154 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 155 * FIXME: the top 17 bits of BR2. 156 */ 157 158 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 159 160 /* 161 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 162 * 163 * For OR2, need: 164 * 64MB mask for AM, OR2[0:7] = 1111 1100 165 * XAM, OR2[17:18] = 11 166 * 9 columns OR2[19-21] = 010 167 * 13 rows OR2[23-25] = 100 168 * EAD set for extra time OR[31] = 1 169 * 170 * 0 4 8 12 16 20 24 28 171 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 172 */ 173 174 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 175 176 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 177 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 178 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 179 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 180 181 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 182 | LSDMR_RFCR5 \ 183 | LSDMR_PRETOACT3 \ 184 | LSDMR_ACTTORW3 \ 185 | LSDMR_BL8 \ 186 | LSDMR_WRC2 \ 187 | LSDMR_CL3 \ 188 | LSDMR_RFEN \ 189 ) 190 191 /* 192 * SDRAM Controller configuration sequence. 193 */ 194 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 195 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 196 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 197 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 198 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 199 200 /* 201 * 32KB, 8-bit wide for ADS config reg 202 */ 203 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 204 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 205 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 206 207 #define CONFIG_SYS_INIT_RAM_LOCK 1 208 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 209 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 210 211 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 212 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 213 214 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 215 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 216 217 /* Serial Port */ 218 #define CONFIG_CONS_INDEX 1 219 #define CONFIG_SYS_NS16550_SERIAL 220 #define CONFIG_SYS_NS16550_REG_SIZE 1 221 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 222 223 #define CONFIG_SYS_BAUDRATE_TABLE \ 224 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 225 226 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 227 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 228 229 /* 230 * I2C 231 */ 232 #define CONFIG_SYS_I2C 233 #define CONFIG_SYS_I2C_FSL 234 #define CONFIG_SYS_FSL_I2C_SPEED 400000 235 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 236 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 237 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 238 239 /* RapidIO MMU */ 240 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 241 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 242 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 243 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 244 245 /* 246 * General PCI 247 * Memory space is mapped 1-1, but I/O space must start from 0. 248 */ 249 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 250 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 251 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 252 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 253 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 254 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 255 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 256 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 257 258 #if defined(CONFIG_PCI) 259 260 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 261 262 #undef CONFIG_EEPRO100 263 #undef CONFIG_TULIP 264 265 #if !defined(CONFIG_PCI_PNP) 266 #define PCI_ENET0_IOADDR 0xe0000000 267 #define PCI_ENET0_MEMADDR 0xe0000000 268 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 269 #endif 270 271 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 272 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 273 274 #endif /* CONFIG_PCI */ 275 276 #if defined(CONFIG_TSEC_ENET) 277 278 #define CONFIG_MII 1 /* MII PHY management */ 279 #define CONFIG_TSEC1 1 280 #define CONFIG_TSEC1_NAME "TSEC0" 281 #define CONFIG_TSEC2 1 282 #define CONFIG_TSEC2_NAME "TSEC1" 283 #define TSEC1_PHY_ADDR 0 284 #define TSEC2_PHY_ADDR 1 285 #define TSEC1_PHYIDX 0 286 #define TSEC2_PHYIDX 0 287 #define TSEC1_FLAGS TSEC_GIGABIT 288 #define TSEC2_FLAGS TSEC_GIGABIT 289 290 #if CONFIG_HAS_FEC 291 #define CONFIG_MPC85XX_FEC 1 292 #define CONFIG_MPC85XX_FEC_NAME "FEC" 293 #define FEC_PHY_ADDR 3 294 #define FEC_PHYIDX 0 295 #define FEC_FLAGS 0 296 #endif 297 298 /* Options are: TSEC[0-1], FEC */ 299 #define CONFIG_ETHPRIME "TSEC0" 300 301 #endif /* CONFIG_TSEC_ENET */ 302 303 /* 304 * Environment 305 */ 306 #ifndef CONFIG_SYS_RAMBOOT 307 #define CONFIG_ENV_IS_IN_FLASH 1 308 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 309 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 310 #define CONFIG_ENV_SIZE 0x2000 311 #else 312 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 313 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 314 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 315 #define CONFIG_ENV_SIZE 0x2000 316 #endif 317 318 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 319 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 320 321 /* 322 * BOOTP options 323 */ 324 #define CONFIG_BOOTP_BOOTFILESIZE 325 #define CONFIG_BOOTP_BOOTPATH 326 #define CONFIG_BOOTP_GATEWAY 327 #define CONFIG_BOOTP_HOSTNAME 328 329 /* 330 * Command line configuration. 331 */ 332 #define CONFIG_CMD_IRQ 333 334 #if defined(CONFIG_PCI) 335 #define CONFIG_CMD_PCI 336 #endif 337 338 #undef CONFIG_WATCHDOG /* watchdog disabled */ 339 340 /* 341 * Miscellaneous configurable options 342 */ 343 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 344 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 345 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 346 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 347 348 #if defined(CONFIG_CMD_KGDB) 349 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 350 #else 351 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 352 #endif 353 354 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 355 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 356 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 357 358 /* 359 * For booting Linux, the board info and command line data 360 * have to be in the first 64 MB of memory, since this is 361 * the maximum mapped by the Linux kernel during initialization. 362 */ 363 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 364 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 365 366 #if defined(CONFIG_CMD_KGDB) 367 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 368 #endif 369 370 /* 371 * Environment Configuration 372 */ 373 374 /* The mac addresses for all ethernet interface */ 375 #if defined(CONFIG_TSEC_ENET) 376 #define CONFIG_HAS_ETH0 377 #define CONFIG_HAS_ETH1 378 #define CONFIG_HAS_ETH2 379 #endif 380 381 #define CONFIG_IPADDR 192.168.1.253 382 383 #define CONFIG_HOSTNAME unknown 384 #define CONFIG_ROOTPATH "/nfsroot" 385 #define CONFIG_BOOTFILE "your.uImage" 386 387 #define CONFIG_SERVERIP 192.168.1.1 388 #define CONFIG_GATEWAYIP 192.168.1.1 389 #define CONFIG_NETMASK 255.255.255.0 390 391 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 392 393 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 394 395 #define CONFIG_BAUDRATE 115200 396 397 #define CONFIG_EXTRA_ENV_SETTINGS \ 398 "netdev=eth0\0" \ 399 "consoledev=ttyS0\0" \ 400 "ramdiskaddr=1000000\0" \ 401 "ramdiskfile=your.ramdisk.u-boot\0" \ 402 "fdtaddr=400000\0" \ 403 "fdtfile=your.fdt.dtb\0" 404 405 #define CONFIG_NFSBOOTCOMMAND \ 406 "setenv bootargs root=/dev/nfs rw " \ 407 "nfsroot=$serverip:$rootpath " \ 408 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 409 "console=$consoledev,$baudrate $othbootargs;" \ 410 "tftp $loadaddr $bootfile;" \ 411 "tftp $fdtaddr $fdtfile;" \ 412 "bootm $loadaddr - $fdtaddr" 413 414 #define CONFIG_RAMBOOTCOMMAND \ 415 "setenv bootargs root=/dev/ram rw " \ 416 "console=$consoledev,$baudrate $othbootargs;" \ 417 "tftp $ramdiskaddr $ramdiskfile;" \ 418 "tftp $loadaddr $bootfile;" \ 419 "tftp $fdtaddr $fdtfile;" \ 420 "bootm $loadaddr $ramdiskaddr $fdtaddr" 421 422 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 423 424 #endif /* __CONFIG_H */ 425