1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8540ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 42 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 43 44 #ifndef CONFIG_HAS_FEC 45 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 46 #endif 47 48 #define CONFIG_PCI 49 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 #define CONFIG_ENV_OVERWRITE 52 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 53 54 /* 55 * sysclk for MPC85xx 56 * 57 * Two valid values are: 58 * 33000000 59 * 66000000 60 * 61 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 62 * is likely the desired value here, so that is now the default. 63 * The board, however, can run at 66MHz. In any event, this value 64 * must match the settings of some switches. Details can be found 65 * in the README.mpc85xxads. 66 * 67 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 68 * 33MHz to accommodate, based on a PCI pin. 69 * Note that PCI-X won't work at 33MHz. 70 */ 71 72 #ifndef CONFIG_SYS_CLK_FREQ 73 #define CONFIG_SYS_CLK_FREQ 33000000 74 #endif 75 76 77 /* 78 * These can be toggled for performance analysis, otherwise use default. 79 */ 80 #define CONFIG_L2_CACHE /* toggle L2 cache */ 81 #define CONFIG_BTB /* toggle branch predition */ 82 83 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 84 #define CONFIG_SYS_MEMTEST_END 0x00400000 85 86 87 /* 88 * Base addresses -- Note these are effective addresses where the 89 * actual resources get mapped (not physical addresses) 90 */ 91 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 92 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 93 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 94 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 95 96 /* DDR Setup */ 97 #define CONFIG_FSL_DDR1 98 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 99 #define CONFIG_DDR_SPD 100 #undef CONFIG_FSL_DDR_INTERACTIVE 101 102 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 103 104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 110 111 /* I2C addresses of SPD EEPROMs */ 112 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 113 114 /* These are used when DDR doesn't use SPD. */ 115 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 116 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 117 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 118 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 119 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 120 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 121 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 122 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 123 124 /* 125 * SDRAM on the Local Bus 126 */ 127 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 128 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 129 130 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 131 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 132 133 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 134 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 135 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 136 #undef CONFIG_SYS_FLASH_CHECKSUM 137 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 138 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 139 140 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 141 142 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 143 #define CONFIG_SYS_RAMBOOT 144 #else 145 #undef CONFIG_SYS_RAMBOOT 146 #endif 147 148 #define CONFIG_FLASH_CFI_DRIVER 149 #define CONFIG_SYS_FLASH_CFI 150 #define CONFIG_SYS_FLASH_EMPTY_INFO 151 152 #undef CONFIG_CLOCKS_IN_MHZ 153 154 155 /* 156 * Local Bus Definitions 157 */ 158 159 /* 160 * Base Register 2 and Option Register 2 configure SDRAM. 161 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 162 * 163 * For BR2, need: 164 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 165 * port-size = 32-bits = BR2[19:20] = 11 166 * no parity checking = BR2[21:22] = 00 167 * SDRAM for MSEL = BR2[24:26] = 011 168 * Valid = BR[31] = 1 169 * 170 * 0 4 8 12 16 20 24 28 171 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 172 * 173 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 174 * FIXME: the top 17 bits of BR2. 175 */ 176 177 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 178 179 /* 180 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 181 * 182 * For OR2, need: 183 * 64MB mask for AM, OR2[0:7] = 1111 1100 184 * XAM, OR2[17:18] = 11 185 * 9 columns OR2[19-21] = 010 186 * 13 rows OR2[23-25] = 100 187 * EAD set for extra time OR[31] = 1 188 * 189 * 0 4 8 12 16 20 24 28 190 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 191 */ 192 193 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 194 195 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 196 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 197 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 198 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 199 200 /* 201 * LSDMR masks 202 */ 203 #define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1)) 204 #define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 205 #define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 206 #define CONFIG_SYS_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 207 #define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 208 #define CONFIG_SYS_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 209 #define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 210 #define CONFIG_SYS_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 211 #define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 212 #define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 213 #define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23)) 214 #define CONFIG_SYS_LBC_LSDMR_WRC2 (2 << (31 - 27)) 215 #define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27)) 216 #define CONFIG_SYS_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 217 #define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31)) 218 219 #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 220 #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 221 #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 222 #define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 223 #define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 224 #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 225 #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 226 #define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 227 228 #define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_BSMA1516 \ 229 | CONFIG_SYS_LBC_LSDMR_RFCR5 \ 230 | CONFIG_SYS_LBC_LSDMR_PRETOACT3 \ 231 | CONFIG_SYS_LBC_LSDMR_ACTTORW3 \ 232 | CONFIG_SYS_LBC_LSDMR_BL8 \ 233 | CONFIG_SYS_LBC_LSDMR_WRC2 \ 234 | CONFIG_SYS_LBC_LSDMR_CL3 \ 235 | CONFIG_SYS_LBC_LSDMR_RFEN \ 236 ) 237 238 /* 239 * SDRAM Controller configuration sequence. 240 */ 241 #define CONFIG_SYS_LBC_LSDMR_1 ( CONFIG_SYS_LBC_LSDMR_COMMON \ 242 | CONFIG_SYS_LBC_LSDMR_OP_PCHALL) 243 #define CONFIG_SYS_LBC_LSDMR_2 ( CONFIG_SYS_LBC_LSDMR_COMMON \ 244 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) 245 #define CONFIG_SYS_LBC_LSDMR_3 ( CONFIG_SYS_LBC_LSDMR_COMMON \ 246 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) 247 #define CONFIG_SYS_LBC_LSDMR_4 ( CONFIG_SYS_LBC_LSDMR_COMMON \ 248 | CONFIG_SYS_LBC_LSDMR_OP_MRW) 249 #define CONFIG_SYS_LBC_LSDMR_5 ( CONFIG_SYS_LBC_LSDMR_COMMON \ 250 | CONFIG_SYS_LBC_LSDMR_OP_NORMAL) 251 252 253 /* 254 * 32KB, 8-bit wide for ADS config reg 255 */ 256 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 257 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 258 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 259 260 #define CONFIG_SYS_INIT_RAM_LOCK 1 261 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 262 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 263 264 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 265 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 266 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 267 268 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 269 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 270 271 /* Serial Port */ 272 #define CONFIG_CONS_INDEX 1 273 #undef CONFIG_SERIAL_SOFTWARE_FIFO 274 #define CONFIG_SYS_NS16550 275 #define CONFIG_SYS_NS16550_SERIAL 276 #define CONFIG_SYS_NS16550_REG_SIZE 1 277 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 278 279 #define CONFIG_SYS_BAUDRATE_TABLE \ 280 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 281 282 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 283 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 284 285 /* Use the HUSH parser */ 286 #define CONFIG_SYS_HUSH_PARSER 287 #ifdef CONFIG_SYS_HUSH_PARSER 288 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 289 #endif 290 291 /* pass open firmware flat tree */ 292 #define CONFIG_OF_LIBFDT 1 293 #define CONFIG_OF_BOARD_SETUP 1 294 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 295 296 #define CONFIG_SYS_64BIT_VSPRINTF 1 297 #define CONFIG_SYS_64BIT_STRTOUL 1 298 299 /* 300 * I2C 301 */ 302 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 303 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 304 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 305 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 306 #define CONFIG_SYS_I2C_SLAVE 0x7F 307 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 308 #define CONFIG_SYS_I2C_OFFSET 0x3000 309 310 /* RapidIO MMU */ 311 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ 312 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 313 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 314 315 /* 316 * General PCI 317 * Memory space is mapped 1-1, but I/O space must start from 0. 318 */ 319 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 320 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 321 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 322 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 323 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 324 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 325 326 #if defined(CONFIG_PCI) 327 328 #define CONFIG_NET_MULTI 329 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 330 331 #undef CONFIG_EEPRO100 332 #undef CONFIG_TULIP 333 334 #if !defined(CONFIG_PCI_PNP) 335 #define PCI_ENET0_IOADDR 0xe0000000 336 #define PCI_ENET0_MEMADDR 0xe0000000 337 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 338 #endif 339 340 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 341 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 342 343 #endif /* CONFIG_PCI */ 344 345 346 #if defined(CONFIG_TSEC_ENET) 347 348 #ifndef CONFIG_NET_MULTI 349 #define CONFIG_NET_MULTI 1 350 #endif 351 352 #define CONFIG_MII 1 /* MII PHY management */ 353 #define CONFIG_TSEC1 1 354 #define CONFIG_TSEC1_NAME "TSEC0" 355 #define CONFIG_TSEC2 1 356 #define CONFIG_TSEC2_NAME "TSEC1" 357 #define TSEC1_PHY_ADDR 0 358 #define TSEC2_PHY_ADDR 1 359 #define TSEC1_PHYIDX 0 360 #define TSEC2_PHYIDX 0 361 #define TSEC1_FLAGS TSEC_GIGABIT 362 #define TSEC2_FLAGS TSEC_GIGABIT 363 364 365 #if CONFIG_HAS_FEC 366 #define CONFIG_MPC85XX_FEC 1 367 #define CONFIG_MPC85XX_FEC_NAME "FEC" 368 #define FEC_PHY_ADDR 3 369 #define FEC_PHYIDX 0 370 #define FEC_FLAGS 0 371 #endif 372 373 /* Options are: TSEC[0-1], FEC */ 374 #define CONFIG_ETHPRIME "TSEC0" 375 376 #endif /* CONFIG_TSEC_ENET */ 377 378 379 /* 380 * Environment 381 */ 382 #ifndef CONFIG_SYS_RAMBOOT 383 #define CONFIG_ENV_IS_IN_FLASH 1 384 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 385 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 386 #define CONFIG_ENV_SIZE 0x2000 387 #else 388 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 389 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 390 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 391 #define CONFIG_ENV_SIZE 0x2000 392 #endif 393 394 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 395 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 396 397 398 /* 399 * BOOTP options 400 */ 401 #define CONFIG_BOOTP_BOOTFILESIZE 402 #define CONFIG_BOOTP_BOOTPATH 403 #define CONFIG_BOOTP_GATEWAY 404 #define CONFIG_BOOTP_HOSTNAME 405 406 407 /* 408 * Command line configuration. 409 */ 410 #include <config_cmd_default.h> 411 412 #define CONFIG_CMD_PING 413 #define CONFIG_CMD_I2C 414 #define CONFIG_CMD_ELF 415 #define CONFIG_CMD_IRQ 416 #define CONFIG_CMD_SETEXPR 417 418 #if defined(CONFIG_PCI) 419 #define CONFIG_CMD_PCI 420 #endif 421 422 #if defined(CONFIG_SYS_RAMBOOT) 423 #undef CONFIG_CMD_ENV 424 #undef CONFIG_CMD_LOADS 425 #endif 426 427 428 #undef CONFIG_WATCHDOG /* watchdog disabled */ 429 430 /* 431 * Miscellaneous configurable options 432 */ 433 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 434 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 435 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 436 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 437 438 #if defined(CONFIG_CMD_KGDB) 439 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 440 #else 441 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 442 #endif 443 444 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 445 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 446 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 447 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 448 449 /* 450 * For booting Linux, the board info and command line data 451 * have to be in the first 8 MB of memory, since this is 452 * the maximum mapped by the Linux kernel during initialization. 453 */ 454 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 455 456 /* 457 * Internal Definitions 458 * 459 * Boot Flags 460 */ 461 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 462 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 463 464 #if defined(CONFIG_CMD_KGDB) 465 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 466 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 467 #endif 468 469 470 /* 471 * Environment Configuration 472 */ 473 474 /* The mac addresses for all ethernet interface */ 475 #if defined(CONFIG_TSEC_ENET) 476 #define CONFIG_HAS_ETH0 477 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 478 #define CONFIG_HAS_ETH1 479 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 480 #define CONFIG_HAS_ETH2 481 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 482 #endif 483 484 #define CONFIG_IPADDR 192.168.1.253 485 486 #define CONFIG_HOSTNAME unknown 487 #define CONFIG_ROOTPATH /nfsroot 488 #define CONFIG_BOOTFILE your.uImage 489 490 #define CONFIG_SERVERIP 192.168.1.1 491 #define CONFIG_GATEWAYIP 192.168.1.1 492 #define CONFIG_NETMASK 255.255.255.0 493 494 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 495 496 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 497 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 498 499 #define CONFIG_BAUDRATE 115200 500 501 #define CONFIG_EXTRA_ENV_SETTINGS \ 502 "netdev=eth0\0" \ 503 "consoledev=ttyS0\0" \ 504 "ramdiskaddr=1000000\0" \ 505 "ramdiskfile=your.ramdisk.u-boot\0" \ 506 "fdtaddr=400000\0" \ 507 "fdtfile=your.fdt.dtb\0" 508 509 #define CONFIG_NFSBOOTCOMMAND \ 510 "setenv bootargs root=/dev/nfs rw " \ 511 "nfsroot=$serverip:$rootpath " \ 512 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 513 "console=$consoledev,$baudrate $othbootargs;" \ 514 "tftp $loadaddr $bootfile;" \ 515 "tftp $fdtaddr $fdtfile;" \ 516 "bootm $loadaddr - $fdtaddr" 517 518 #define CONFIG_RAMBOOTCOMMAND \ 519 "setenv bootargs root=/dev/ram rw " \ 520 "console=$consoledev,$baudrate $othbootargs;" \ 521 "tftp $ramdiskaddr $ramdiskfile;" \ 522 "tftp $loadaddr $bootfile;" \ 523 "tftp $fdtaddr $fdtfile;" \ 524 "bootm $loadaddr $ramdiskaddr $fdtaddr" 525 526 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 527 528 #endif /* __CONFIG_H */ 529