1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8540ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 42 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 43 44 /* 45 * default CCARBAR is at 0xff700000 46 * assume U-Boot is less than 0.5MB 47 */ 48 #define CONFIG_SYS_TEXT_BASE 0xfff80000 49 50 #ifndef CONFIG_HAS_FEC 51 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 52 #endif 53 54 #define CONFIG_PCI 55 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 56 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 57 #define CONFIG_ENV_OVERWRITE 58 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 59 60 /* 61 * sysclk for MPC85xx 62 * 63 * Two valid values are: 64 * 33000000 65 * 66000000 66 * 67 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 68 * is likely the desired value here, so that is now the default. 69 * The board, however, can run at 66MHz. In any event, this value 70 * must match the settings of some switches. Details can be found 71 * in the README.mpc85xxads. 72 * 73 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 74 * 33MHz to accommodate, based on a PCI pin. 75 * Note that PCI-X won't work at 33MHz. 76 */ 77 78 #ifndef CONFIG_SYS_CLK_FREQ 79 #define CONFIG_SYS_CLK_FREQ 33000000 80 #endif 81 82 83 /* 84 * These can be toggled for performance analysis, otherwise use default. 85 */ 86 #define CONFIG_L2_CACHE /* toggle L2 cache */ 87 #define CONFIG_BTB /* toggle branch predition */ 88 89 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 90 #define CONFIG_SYS_MEMTEST_END 0x00400000 91 92 #define CONFIG_SYS_CCSRBAR 0xe0000000 93 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 94 95 /* DDR Setup */ 96 #define CONFIG_FSL_DDR1 97 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 98 #define CONFIG_DDR_SPD 99 #undef CONFIG_FSL_DDR_INTERACTIVE 100 101 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 102 103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105 106 #define CONFIG_NUM_DDR_CONTROLLERS 1 107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 109 110 /* I2C addresses of SPD EEPROMs */ 111 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 112 113 /* These are used when DDR doesn't use SPD. */ 114 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 115 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 116 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 117 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 118 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 119 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 120 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 121 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 122 123 /* 124 * SDRAM on the Local Bus 125 */ 126 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 127 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 128 129 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 130 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 131 132 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 133 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 134 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 135 #undef CONFIG_SYS_FLASH_CHECKSUM 136 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 137 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 138 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 140 141 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 142 #define CONFIG_SYS_RAMBOOT 143 #else 144 #undef CONFIG_SYS_RAMBOOT 145 #endif 146 147 #define CONFIG_FLASH_CFI_DRIVER 148 #define CONFIG_SYS_FLASH_CFI 149 #define CONFIG_SYS_FLASH_EMPTY_INFO 150 151 #undef CONFIG_CLOCKS_IN_MHZ 152 153 154 /* 155 * Local Bus Definitions 156 */ 157 158 /* 159 * Base Register 2 and Option Register 2 configure SDRAM. 160 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 161 * 162 * For BR2, need: 163 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 164 * port-size = 32-bits = BR2[19:20] = 11 165 * no parity checking = BR2[21:22] = 00 166 * SDRAM for MSEL = BR2[24:26] = 011 167 * Valid = BR[31] = 1 168 * 169 * 0 4 8 12 16 20 24 28 170 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 171 * 172 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 173 * FIXME: the top 17 bits of BR2. 174 */ 175 176 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 177 178 /* 179 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 180 * 181 * For OR2, need: 182 * 64MB mask for AM, OR2[0:7] = 1111 1100 183 * XAM, OR2[17:18] = 11 184 * 9 columns OR2[19-21] = 010 185 * 13 rows OR2[23-25] = 100 186 * EAD set for extra time OR[31] = 1 187 * 188 * 0 4 8 12 16 20 24 28 189 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 190 */ 191 192 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 193 194 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 195 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 196 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 197 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 198 199 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 200 | LSDMR_RFCR5 \ 201 | LSDMR_PRETOACT3 \ 202 | LSDMR_ACTTORW3 \ 203 | LSDMR_BL8 \ 204 | LSDMR_WRC2 \ 205 | LSDMR_CL3 \ 206 | LSDMR_RFEN \ 207 ) 208 209 /* 210 * SDRAM Controller configuration sequence. 211 */ 212 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 213 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 214 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 215 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 216 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 217 218 219 /* 220 * 32KB, 8-bit wide for ADS config reg 221 */ 222 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 223 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 224 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 225 226 #define CONFIG_SYS_INIT_RAM_LOCK 1 227 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 228 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 229 230 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 232 233 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 234 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 235 236 /* Serial Port */ 237 #define CONFIG_CONS_INDEX 1 238 #define CONFIG_SYS_NS16550 239 #define CONFIG_SYS_NS16550_SERIAL 240 #define CONFIG_SYS_NS16550_REG_SIZE 1 241 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 242 243 #define CONFIG_SYS_BAUDRATE_TABLE \ 244 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 245 246 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 247 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 248 249 /* Use the HUSH parser */ 250 #define CONFIG_SYS_HUSH_PARSER 251 #ifdef CONFIG_SYS_HUSH_PARSER 252 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 253 #endif 254 255 /* pass open firmware flat tree */ 256 #define CONFIG_OF_LIBFDT 1 257 #define CONFIG_OF_BOARD_SETUP 1 258 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 259 260 /* 261 * I2C 262 */ 263 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 264 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 265 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 266 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 267 #define CONFIG_SYS_I2C_SLAVE 0x7F 268 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 269 #define CONFIG_SYS_I2C_OFFSET 0x3000 270 271 /* RapidIO MMU */ 272 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 273 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 274 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 275 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 276 277 /* 278 * General PCI 279 * Memory space is mapped 1-1, but I/O space must start from 0. 280 */ 281 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 282 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 283 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 284 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 285 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 286 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 287 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 288 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 289 290 #if defined(CONFIG_PCI) 291 292 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 293 294 #undef CONFIG_EEPRO100 295 #undef CONFIG_TULIP 296 297 #if !defined(CONFIG_PCI_PNP) 298 #define PCI_ENET0_IOADDR 0xe0000000 299 #define PCI_ENET0_MEMADDR 0xe0000000 300 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 301 #endif 302 303 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 304 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 305 306 #endif /* CONFIG_PCI */ 307 308 309 #if defined(CONFIG_TSEC_ENET) 310 311 #define CONFIG_MII 1 /* MII PHY management */ 312 #define CONFIG_TSEC1 1 313 #define CONFIG_TSEC1_NAME "TSEC0" 314 #define CONFIG_TSEC2 1 315 #define CONFIG_TSEC2_NAME "TSEC1" 316 #define TSEC1_PHY_ADDR 0 317 #define TSEC2_PHY_ADDR 1 318 #define TSEC1_PHYIDX 0 319 #define TSEC2_PHYIDX 0 320 #define TSEC1_FLAGS TSEC_GIGABIT 321 #define TSEC2_FLAGS TSEC_GIGABIT 322 323 324 #if CONFIG_HAS_FEC 325 #define CONFIG_MPC85XX_FEC 1 326 #define CONFIG_MPC85XX_FEC_NAME "FEC" 327 #define FEC_PHY_ADDR 3 328 #define FEC_PHYIDX 0 329 #define FEC_FLAGS 0 330 #endif 331 332 /* Options are: TSEC[0-1], FEC */ 333 #define CONFIG_ETHPRIME "TSEC0" 334 335 #endif /* CONFIG_TSEC_ENET */ 336 337 338 /* 339 * Environment 340 */ 341 #ifndef CONFIG_SYS_RAMBOOT 342 #define CONFIG_ENV_IS_IN_FLASH 1 343 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 344 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 345 #define CONFIG_ENV_SIZE 0x2000 346 #else 347 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 348 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 349 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 350 #define CONFIG_ENV_SIZE 0x2000 351 #endif 352 353 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 354 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 355 356 357 /* 358 * BOOTP options 359 */ 360 #define CONFIG_BOOTP_BOOTFILESIZE 361 #define CONFIG_BOOTP_BOOTPATH 362 #define CONFIG_BOOTP_GATEWAY 363 #define CONFIG_BOOTP_HOSTNAME 364 365 366 /* 367 * Command line configuration. 368 */ 369 #include <config_cmd_default.h> 370 371 #define CONFIG_CMD_PING 372 #define CONFIG_CMD_I2C 373 #define CONFIG_CMD_ELF 374 #define CONFIG_CMD_IRQ 375 #define CONFIG_CMD_SETEXPR 376 377 #if defined(CONFIG_PCI) 378 #define CONFIG_CMD_PCI 379 #endif 380 381 #if defined(CONFIG_SYS_RAMBOOT) 382 #undef CONFIG_CMD_SAVEENV 383 #undef CONFIG_CMD_LOADS 384 #endif 385 386 387 #undef CONFIG_WATCHDOG /* watchdog disabled */ 388 389 /* 390 * Miscellaneous configurable options 391 */ 392 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 393 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 394 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 395 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 396 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 397 398 #if defined(CONFIG_CMD_KGDB) 399 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 400 #else 401 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 402 #endif 403 404 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 405 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 406 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 407 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 408 409 /* 410 * For booting Linux, the board info and command line data 411 * have to be in the first 64 MB of memory, since this is 412 * the maximum mapped by the Linux kernel during initialization. 413 */ 414 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 415 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 416 417 #if defined(CONFIG_CMD_KGDB) 418 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 419 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 420 #endif 421 422 423 /* 424 * Environment Configuration 425 */ 426 427 /* The mac addresses for all ethernet interface */ 428 #if defined(CONFIG_TSEC_ENET) 429 #define CONFIG_HAS_ETH0 430 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 431 #define CONFIG_HAS_ETH1 432 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 433 #define CONFIG_HAS_ETH2 434 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 435 #endif 436 437 #define CONFIG_IPADDR 192.168.1.253 438 439 #define CONFIG_HOSTNAME unknown 440 #define CONFIG_ROOTPATH "/nfsroot" 441 #define CONFIG_BOOTFILE "your.uImage" 442 443 #define CONFIG_SERVERIP 192.168.1.1 444 #define CONFIG_GATEWAYIP 192.168.1.1 445 #define CONFIG_NETMASK 255.255.255.0 446 447 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 448 449 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 450 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 451 452 #define CONFIG_BAUDRATE 115200 453 454 #define CONFIG_EXTRA_ENV_SETTINGS \ 455 "netdev=eth0\0" \ 456 "consoledev=ttyS0\0" \ 457 "ramdiskaddr=1000000\0" \ 458 "ramdiskfile=your.ramdisk.u-boot\0" \ 459 "fdtaddr=400000\0" \ 460 "fdtfile=your.fdt.dtb\0" 461 462 #define CONFIG_NFSBOOTCOMMAND \ 463 "setenv bootargs root=/dev/nfs rw " \ 464 "nfsroot=$serverip:$rootpath " \ 465 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 466 "console=$consoledev,$baudrate $othbootargs;" \ 467 "tftp $loadaddr $bootfile;" \ 468 "tftp $fdtaddr $fdtfile;" \ 469 "bootm $loadaddr - $fdtaddr" 470 471 #define CONFIG_RAMBOOTCOMMAND \ 472 "setenv bootargs root=/dev/ram rw " \ 473 "console=$consoledev,$baudrate $othbootargs;" \ 474 "tftp $ramdiskaddr $ramdiskfile;" \ 475 "tftp $loadaddr $bootfile;" \ 476 "tftp $fdtaddr $fdtfile;" \ 477 "bootm $loadaddr $ramdiskaddr $fdtaddr" 478 479 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 480 481 #endif /* __CONFIG_H */ 482