1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8540ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* 22 * default CCARBAR is at 0xff700000 23 * assume U-Boot is less than 0.5MB 24 */ 25 #define CONFIG_SYS_TEXT_BASE 0xfff80000 26 27 #ifndef CONFIG_HAS_FEC 28 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 29 #endif 30 31 #define CONFIG_PCI_INDIRECT_BRIDGE 32 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 33 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 34 #define CONFIG_ENV_OVERWRITE 35 36 /* 37 * sysclk for MPC85xx 38 * 39 * Two valid values are: 40 * 33000000 41 * 66000000 42 * 43 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 44 * is likely the desired value here, so that is now the default. 45 * The board, however, can run at 66MHz. In any event, this value 46 * must match the settings of some switches. Details can be found 47 * in the README.mpc85xxads. 48 * 49 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 50 * 33MHz to accommodate, based on a PCI pin. 51 * Note that PCI-X won't work at 33MHz. 52 */ 53 54 #ifndef CONFIG_SYS_CLK_FREQ 55 #define CONFIG_SYS_CLK_FREQ 33000000 56 #endif 57 58 /* 59 * These can be toggled for performance analysis, otherwise use default. 60 */ 61 #define CONFIG_L2_CACHE /* toggle L2 cache */ 62 #define CONFIG_BTB /* toggle branch predition */ 63 64 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 65 #define CONFIG_SYS_MEMTEST_END 0x00400000 66 67 #define CONFIG_SYS_CCSRBAR 0xe0000000 68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 69 70 /* DDR Setup */ 71 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 72 #define CONFIG_DDR_SPD 73 #undef CONFIG_FSL_DDR_INTERACTIVE 74 75 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 76 77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 78 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 79 80 #define CONFIG_NUM_DDR_CONTROLLERS 1 81 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 82 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 83 84 /* I2C addresses of SPD EEPROMs */ 85 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 86 87 /* These are used when DDR doesn't use SPD. */ 88 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 89 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 91 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 92 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 93 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 94 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 95 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 96 97 /* 98 * SDRAM on the Local Bus 99 */ 100 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 101 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 102 103 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 104 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 105 106 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 107 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 108 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 109 #undef CONFIG_SYS_FLASH_CHECKSUM 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 112 113 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 114 115 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 116 #define CONFIG_SYS_RAMBOOT 117 #else 118 #undef CONFIG_SYS_RAMBOOT 119 #endif 120 121 #define CONFIG_FLASH_CFI_DRIVER 122 #define CONFIG_SYS_FLASH_CFI 123 #define CONFIG_SYS_FLASH_EMPTY_INFO 124 125 #undef CONFIG_CLOCKS_IN_MHZ 126 127 /* 128 * Local Bus Definitions 129 */ 130 131 /* 132 * Base Register 2 and Option Register 2 configure SDRAM. 133 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 134 * 135 * For BR2, need: 136 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 137 * port-size = 32-bits = BR2[19:20] = 11 138 * no parity checking = BR2[21:22] = 00 139 * SDRAM for MSEL = BR2[24:26] = 011 140 * Valid = BR[31] = 1 141 * 142 * 0 4 8 12 16 20 24 28 143 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 144 * 145 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 146 * FIXME: the top 17 bits of BR2. 147 */ 148 149 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 150 151 /* 152 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 153 * 154 * For OR2, need: 155 * 64MB mask for AM, OR2[0:7] = 1111 1100 156 * XAM, OR2[17:18] = 11 157 * 9 columns OR2[19-21] = 010 158 * 13 rows OR2[23-25] = 100 159 * EAD set for extra time OR[31] = 1 160 * 161 * 0 4 8 12 16 20 24 28 162 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 163 */ 164 165 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 166 167 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 168 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 169 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 170 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 171 172 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 173 | LSDMR_RFCR5 \ 174 | LSDMR_PRETOACT3 \ 175 | LSDMR_ACTTORW3 \ 176 | LSDMR_BL8 \ 177 | LSDMR_WRC2 \ 178 | LSDMR_CL3 \ 179 | LSDMR_RFEN \ 180 ) 181 182 /* 183 * SDRAM Controller configuration sequence. 184 */ 185 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 186 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 187 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 188 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 189 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 190 191 /* 192 * 32KB, 8-bit wide for ADS config reg 193 */ 194 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 195 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 196 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 197 198 #define CONFIG_SYS_INIT_RAM_LOCK 1 199 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 200 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 201 202 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 203 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 204 205 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 206 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 207 208 /* Serial Port */ 209 #define CONFIG_CONS_INDEX 1 210 #define CONFIG_SYS_NS16550_SERIAL 211 #define CONFIG_SYS_NS16550_REG_SIZE 1 212 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 213 214 #define CONFIG_SYS_BAUDRATE_TABLE \ 215 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 216 217 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 218 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 219 220 /* 221 * I2C 222 */ 223 #define CONFIG_SYS_I2C 224 #define CONFIG_SYS_I2C_FSL 225 #define CONFIG_SYS_FSL_I2C_SPEED 400000 226 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 227 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 228 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 229 230 /* RapidIO MMU */ 231 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 232 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 233 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 234 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 235 236 /* 237 * General PCI 238 * Memory space is mapped 1-1, but I/O space must start from 0. 239 */ 240 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 241 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 242 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 243 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 244 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 245 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 246 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 247 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 248 249 #if defined(CONFIG_PCI) 250 #undef CONFIG_EEPRO100 251 #undef CONFIG_TULIP 252 253 #if !defined(CONFIG_PCI_PNP) 254 #define PCI_ENET0_IOADDR 0xe0000000 255 #define PCI_ENET0_MEMADDR 0xe0000000 256 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 257 #endif 258 259 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 260 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 261 262 #endif /* CONFIG_PCI */ 263 264 #if defined(CONFIG_TSEC_ENET) 265 266 #define CONFIG_MII 1 /* MII PHY management */ 267 #define CONFIG_TSEC1 1 268 #define CONFIG_TSEC1_NAME "TSEC0" 269 #define CONFIG_TSEC2 1 270 #define CONFIG_TSEC2_NAME "TSEC1" 271 #define TSEC1_PHY_ADDR 0 272 #define TSEC2_PHY_ADDR 1 273 #define TSEC1_PHYIDX 0 274 #define TSEC2_PHYIDX 0 275 #define TSEC1_FLAGS TSEC_GIGABIT 276 #define TSEC2_FLAGS TSEC_GIGABIT 277 278 #if CONFIG_HAS_FEC 279 #define CONFIG_MPC85XX_FEC 1 280 #define CONFIG_MPC85XX_FEC_NAME "FEC" 281 #define FEC_PHY_ADDR 3 282 #define FEC_PHYIDX 0 283 #define FEC_FLAGS 0 284 #endif 285 286 /* Options are: TSEC[0-1], FEC */ 287 #define CONFIG_ETHPRIME "TSEC0" 288 289 #endif /* CONFIG_TSEC_ENET */ 290 291 /* 292 * Environment 293 */ 294 #ifndef CONFIG_SYS_RAMBOOT 295 #define CONFIG_ENV_IS_IN_FLASH 1 296 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 297 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 298 #define CONFIG_ENV_SIZE 0x2000 299 #else 300 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 301 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 302 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 303 #define CONFIG_ENV_SIZE 0x2000 304 #endif 305 306 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 307 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 308 309 /* 310 * BOOTP options 311 */ 312 #define CONFIG_BOOTP_BOOTFILESIZE 313 #define CONFIG_BOOTP_BOOTPATH 314 #define CONFIG_BOOTP_GATEWAY 315 #define CONFIG_BOOTP_HOSTNAME 316 317 /* 318 * Command line configuration. 319 */ 320 #define CONFIG_CMD_IRQ 321 322 #if defined(CONFIG_PCI) 323 #define CONFIG_CMD_PCI 324 #endif 325 326 #undef CONFIG_WATCHDOG /* watchdog disabled */ 327 328 /* 329 * Miscellaneous configurable options 330 */ 331 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 332 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 333 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 334 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 335 336 #if defined(CONFIG_CMD_KGDB) 337 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 338 #else 339 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 340 #endif 341 342 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 343 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 344 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 345 346 /* 347 * For booting Linux, the board info and command line data 348 * have to be in the first 64 MB of memory, since this is 349 * the maximum mapped by the Linux kernel during initialization. 350 */ 351 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 352 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 353 354 #if defined(CONFIG_CMD_KGDB) 355 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 356 #endif 357 358 /* 359 * Environment Configuration 360 */ 361 362 /* The mac addresses for all ethernet interface */ 363 #if defined(CONFIG_TSEC_ENET) 364 #define CONFIG_HAS_ETH0 365 #define CONFIG_HAS_ETH1 366 #define CONFIG_HAS_ETH2 367 #endif 368 369 #define CONFIG_IPADDR 192.168.1.253 370 371 #define CONFIG_HOSTNAME unknown 372 #define CONFIG_ROOTPATH "/nfsroot" 373 #define CONFIG_BOOTFILE "your.uImage" 374 375 #define CONFIG_SERVERIP 192.168.1.1 376 #define CONFIG_GATEWAYIP 192.168.1.1 377 #define CONFIG_NETMASK 255.255.255.0 378 379 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 380 381 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 382 383 #define CONFIG_BAUDRATE 115200 384 385 #define CONFIG_EXTRA_ENV_SETTINGS \ 386 "netdev=eth0\0" \ 387 "consoledev=ttyS0\0" \ 388 "ramdiskaddr=1000000\0" \ 389 "ramdiskfile=your.ramdisk.u-boot\0" \ 390 "fdtaddr=400000\0" \ 391 "fdtfile=your.fdt.dtb\0" 392 393 #define CONFIG_NFSBOOTCOMMAND \ 394 "setenv bootargs root=/dev/nfs rw " \ 395 "nfsroot=$serverip:$rootpath " \ 396 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 397 "console=$consoledev,$baudrate $othbootargs;" \ 398 "tftp $loadaddr $bootfile;" \ 399 "tftp $fdtaddr $fdtfile;" \ 400 "bootm $loadaddr - $fdtaddr" 401 402 #define CONFIG_RAMBOOTCOMMAND \ 403 "setenv bootargs root=/dev/ram rw " \ 404 "console=$consoledev,$baudrate $othbootargs;" \ 405 "tftp $ramdiskaddr $ramdiskfile;" \ 406 "tftp $loadaddr $bootfile;" \ 407 "tftp $fdtaddr $fdtfile;" \ 408 "bootm $loadaddr $ramdiskaddr $fdtaddr" 409 410 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 411 412 #endif /* __CONFIG_H */ 413