1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8540ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* 22 * default CCARBAR is at 0xff700000 23 * assume U-Boot is less than 0.5MB 24 */ 25 26 #ifndef CONFIG_HAS_FEC 27 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 28 #endif 29 30 #define CONFIG_PCI_INDIRECT_BRIDGE 31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 32 #define CONFIG_ENV_OVERWRITE 33 34 /* 35 * sysclk for MPC85xx 36 * 37 * Two valid values are: 38 * 33000000 39 * 66000000 40 * 41 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 42 * is likely the desired value here, so that is now the default. 43 * The board, however, can run at 66MHz. In any event, this value 44 * must match the settings of some switches. Details can be found 45 * in the README.mpc85xxads. 46 * 47 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 48 * 33MHz to accommodate, based on a PCI pin. 49 * Note that PCI-X won't work at 33MHz. 50 */ 51 52 #ifndef CONFIG_SYS_CLK_FREQ 53 #define CONFIG_SYS_CLK_FREQ 33000000 54 #endif 55 56 /* 57 * These can be toggled for performance analysis, otherwise use default. 58 */ 59 #define CONFIG_L2_CACHE /* toggle L2 cache */ 60 #define CONFIG_BTB /* toggle branch predition */ 61 62 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 63 #define CONFIG_SYS_MEMTEST_END 0x00400000 64 65 #define CONFIG_SYS_CCSRBAR 0xe0000000 66 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 67 68 /* DDR Setup */ 69 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 70 #define CONFIG_DDR_SPD 71 #undef CONFIG_FSL_DDR_INTERACTIVE 72 73 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 74 75 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 76 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 77 78 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 79 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 80 81 /* I2C addresses of SPD EEPROMs */ 82 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 83 84 /* These are used when DDR doesn't use SPD. */ 85 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 86 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 87 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 88 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 89 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 90 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 91 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 92 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 93 94 /* 95 * SDRAM on the Local Bus 96 */ 97 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 98 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 99 100 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 101 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 102 103 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 104 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 105 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 106 #undef CONFIG_SYS_FLASH_CHECKSUM 107 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 108 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 109 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 111 112 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 113 #define CONFIG_SYS_RAMBOOT 114 #else 115 #undef CONFIG_SYS_RAMBOOT 116 #endif 117 118 #define CONFIG_FLASH_CFI_DRIVER 119 #define CONFIG_SYS_FLASH_CFI 120 #define CONFIG_SYS_FLASH_EMPTY_INFO 121 122 #undef CONFIG_CLOCKS_IN_MHZ 123 124 /* 125 * Local Bus Definitions 126 */ 127 128 /* 129 * Base Register 2 and Option Register 2 configure SDRAM. 130 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 131 * 132 * For BR2, need: 133 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 134 * port-size = 32-bits = BR2[19:20] = 11 135 * no parity checking = BR2[21:22] = 00 136 * SDRAM for MSEL = BR2[24:26] = 011 137 * Valid = BR[31] = 1 138 * 139 * 0 4 8 12 16 20 24 28 140 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 141 * 142 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 143 * FIXME: the top 17 bits of BR2. 144 */ 145 146 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 147 148 /* 149 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 150 * 151 * For OR2, need: 152 * 64MB mask for AM, OR2[0:7] = 1111 1100 153 * XAM, OR2[17:18] = 11 154 * 9 columns OR2[19-21] = 010 155 * 13 rows OR2[23-25] = 100 156 * EAD set for extra time OR[31] = 1 157 * 158 * 0 4 8 12 16 20 24 28 159 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 160 */ 161 162 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 163 164 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 165 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 166 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 167 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 168 169 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 170 | LSDMR_RFCR5 \ 171 | LSDMR_PRETOACT3 \ 172 | LSDMR_ACTTORW3 \ 173 | LSDMR_BL8 \ 174 | LSDMR_WRC2 \ 175 | LSDMR_CL3 \ 176 | LSDMR_RFEN \ 177 ) 178 179 /* 180 * SDRAM Controller configuration sequence. 181 */ 182 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 183 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 184 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 185 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 186 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 187 188 /* 189 * 32KB, 8-bit wide for ADS config reg 190 */ 191 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 192 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 193 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 194 195 #define CONFIG_SYS_INIT_RAM_LOCK 1 196 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 197 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 198 199 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 200 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 201 202 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 203 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 204 205 /* Serial Port */ 206 #define CONFIG_SYS_NS16550_SERIAL 207 #define CONFIG_SYS_NS16550_REG_SIZE 1 208 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 209 210 #define CONFIG_SYS_BAUDRATE_TABLE \ 211 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 212 213 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 214 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 215 216 /* 217 * I2C 218 */ 219 #define CONFIG_SYS_I2C 220 #define CONFIG_SYS_I2C_FSL 221 #define CONFIG_SYS_FSL_I2C_SPEED 400000 222 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 223 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 224 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 225 226 /* RapidIO MMU */ 227 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 228 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 229 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 230 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 231 232 /* 233 * General PCI 234 * Memory space is mapped 1-1, but I/O space must start from 0. 235 */ 236 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 237 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 238 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 239 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 240 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 241 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 242 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 243 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 244 245 #if defined(CONFIG_PCI) 246 #undef CONFIG_EEPRO100 247 #undef CONFIG_TULIP 248 249 #if !defined(CONFIG_PCI_PNP) 250 #define PCI_ENET0_IOADDR 0xe0000000 251 #define PCI_ENET0_MEMADDR 0xe0000000 252 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 253 #endif 254 255 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 256 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 257 258 #endif /* CONFIG_PCI */ 259 260 #if defined(CONFIG_TSEC_ENET) 261 262 #define CONFIG_MII 1 /* MII PHY management */ 263 #define CONFIG_TSEC1 1 264 #define CONFIG_TSEC1_NAME "TSEC0" 265 #define CONFIG_TSEC2 1 266 #define CONFIG_TSEC2_NAME "TSEC1" 267 #define TSEC1_PHY_ADDR 0 268 #define TSEC2_PHY_ADDR 1 269 #define TSEC1_PHYIDX 0 270 #define TSEC2_PHYIDX 0 271 #define TSEC1_FLAGS TSEC_GIGABIT 272 #define TSEC2_FLAGS TSEC_GIGABIT 273 274 #if CONFIG_HAS_FEC 275 #define CONFIG_MPC85XX_FEC 1 276 #define CONFIG_MPC85XX_FEC_NAME "FEC" 277 #define FEC_PHY_ADDR 3 278 #define FEC_PHYIDX 0 279 #define FEC_FLAGS 0 280 #endif 281 282 /* Options are: TSEC[0-1], FEC */ 283 #define CONFIG_ETHPRIME "TSEC0" 284 285 #endif /* CONFIG_TSEC_ENET */ 286 287 /* 288 * Environment 289 */ 290 #ifndef CONFIG_SYS_RAMBOOT 291 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 292 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 293 #define CONFIG_ENV_SIZE 0x2000 294 #else 295 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 296 #define CONFIG_ENV_SIZE 0x2000 297 #endif 298 299 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 300 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 301 302 /* 303 * BOOTP options 304 */ 305 #define CONFIG_BOOTP_BOOTFILESIZE 306 307 /* 308 * Command line configuration. 309 */ 310 311 #undef CONFIG_WATCHDOG /* watchdog disabled */ 312 313 /* 314 * Miscellaneous configurable options 315 */ 316 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 317 318 /* 319 * For booting Linux, the board info and command line data 320 * have to be in the first 64 MB of memory, since this is 321 * the maximum mapped by the Linux kernel during initialization. 322 */ 323 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 324 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 325 326 #if defined(CONFIG_CMD_KGDB) 327 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 328 #endif 329 330 /* 331 * Environment Configuration 332 */ 333 334 /* The mac addresses for all ethernet interface */ 335 #if defined(CONFIG_TSEC_ENET) 336 #define CONFIG_HAS_ETH0 337 #define CONFIG_HAS_ETH1 338 #define CONFIG_HAS_ETH2 339 #endif 340 341 #define CONFIG_IPADDR 192.168.1.253 342 343 #define CONFIG_HOSTNAME "unknown" 344 #define CONFIG_ROOTPATH "/nfsroot" 345 #define CONFIG_BOOTFILE "your.uImage" 346 347 #define CONFIG_SERVERIP 192.168.1.1 348 #define CONFIG_GATEWAYIP 192.168.1.1 349 #define CONFIG_NETMASK 255.255.255.0 350 351 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 352 353 #define CONFIG_EXTRA_ENV_SETTINGS \ 354 "netdev=eth0\0" \ 355 "consoledev=ttyS0\0" \ 356 "ramdiskaddr=1000000\0" \ 357 "ramdiskfile=your.ramdisk.u-boot\0" \ 358 "fdtaddr=400000\0" \ 359 "fdtfile=your.fdt.dtb\0" 360 361 #define CONFIG_NFSBOOTCOMMAND \ 362 "setenv bootargs root=/dev/nfs rw " \ 363 "nfsroot=$serverip:$rootpath " \ 364 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 365 "console=$consoledev,$baudrate $othbootargs;" \ 366 "tftp $loadaddr $bootfile;" \ 367 "tftp $fdtaddr $fdtfile;" \ 368 "bootm $loadaddr - $fdtaddr" 369 370 #define CONFIG_RAMBOOTCOMMAND \ 371 "setenv bootargs root=/dev/ram rw " \ 372 "console=$consoledev,$baudrate $othbootargs;" \ 373 "tftp $ramdiskaddr $ramdiskfile;" \ 374 "tftp $loadaddr $bootfile;" \ 375 "tftp $fdtaddr $fdtfile;" \ 376 "bootm $loadaddr $ramdiskaddr $fdtaddr" 377 378 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 379 380 #endif /* __CONFIG_H */ 381