1 /* 2 * (C) Copyright 2002,2003 Motorola,Inc. 3 * Xianghua Xiao <X.Xiao@motorola.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* mpc8540ads board configuration file */ 25 /* please refer to doc/README.mpc85xxads for more info */ 26 /* make sure you change the MAC address and other network params first, 27 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file 28 */ 29 30 #ifndef __CONFIG_H 31 #define __CONFIG_H 32 33 /* High Level Configuration Options */ 34 #define CONFIG_BOOKE 1 /* BOOKE */ 35 #define CONFIG_E500 1 /* BOOKE e500 family */ 36 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 37 #define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1 Chip */ 38 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 39 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific*/ 40 41 #undef CONFIG_PCI /* pci ethernet support */ 42 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 43 #define CONFIG_ENV_OVERWRITE 44 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 45 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 46 47 #if defined(CONFIG_MPC85xx_REV1) 48 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 49 #endif 50 51 /* Using Localbus SDRAM to emulate flash before we can program the flash, 52 * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. 53 */ 54 #undef CONFIG_RAM_AS_FLASH 55 56 #if !defined(CONFIG_PCI) /* some PCI card is 33Mhz only */ 57 #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */ 58 #else 59 #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ 60 #endif 61 62 #if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */ 63 #define CONFIG_DDR_SETTING 64 #endif 65 66 /* below can be toggled for performance analysis. otherwise use default */ 67 #define CONFIG_L2_CACHE /* toggle L2 cache */ 68 #undef CONFIG_BTB /* toggle branch predition */ 69 #undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ 70 71 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 72 73 #undef CFG_DRAM_TEST /* memory test, takes time */ 74 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 75 #define CFG_MEMTEST_END 0x00400000 76 77 #if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) 78 #error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both." 79 #endif 80 81 /* 82 * Base addresses -- Note these are effective addresses where the 83 * actual resources get mapped (not physical addresses) 84 */ 85 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 86 #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ 87 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 88 89 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 90 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 91 #define CFG_SDRAM_SIZE 128 /* DDR is now 128MB */ 92 93 #if defined(CONFIG_RAM_AS_FLASH) 94 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ 95 #else 96 #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ 97 #endif 98 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 99 100 #if defined(CONFIG_RAM_AS_FLASH) 101 #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ 102 #define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ 103 #else /* Boot from real Flash */ 104 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 105 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 106 #endif 107 108 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 109 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 110 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 111 #undef CFG_FLASH_CHECKSUM 112 #define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/ 113 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/ 114 115 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 116 117 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 118 #define CFG_RAMBOOT 119 #else 120 #undef CFG_RAMBOOT 121 #endif 122 123 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 124 125 #if defined(CONFIG_DDR_SETTING) 126 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 127 #define CFG_DDR_CS0_CONFIG 0x80000002 128 #define CFG_DDR_TIMING_1 0x37344321 129 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/ 130 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/ 131 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 132 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/ 133 #endif 134 135 #undef CONFIG_CLOCKS_IN_MHZ 136 137 /* local bus definitions */ 138 #define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ 139 #define CFG_OR2_PRELIM 0xfc006901 140 #define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/ 141 #define CFG_LBC_LBCR 0x00000000 142 #define CFG_LBC_LSRT 0x20000000 143 #define CFG_LBC_MRTPR 0x20000000 144 #define CFG_LBC_LSDMR_1 0x2861b723 145 #define CFG_LBC_LSDMR_2 0x0861b723 146 #define CFG_LBC_LSDMR_3 0x0861b723 147 #define CFG_LBC_LSDMR_4 0x1861b723 148 #define CFG_LBC_LSDMR_5 0x4061b723 149 150 #if defined(CONFIG_RAM_AS_FLASH) 151 #define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ 152 #else 153 #define CFG_BR4_PRELIM 0xfc000801 /* 32KB, 8-bit wide for ADS config reg */ 154 #endif 155 #define CFG_OR4_PRELIM 0xffffe1f1 156 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 157 158 #define CONFIG_L1_INIT_RAM 159 #define CFG_INIT_RAM_LOCK 1 160 #define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ 161 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 162 163 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 164 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 165 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 166 167 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 168 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 169 170 /* Serial Port */ 171 #define CONFIG_CONS_INDEX 1 172 #undef CONFIG_SERIAL_SOFTWARE_FIFO 173 #define CFG_NS16550 174 #define CFG_NS16550_SERIAL 175 #define CFG_NS16550_REG_SIZE 1 176 #define CFG_NS16550_CLK get_bus_freq(0) 177 #define CONFIG_BAUDRATE 115200 178 179 #define CFG_BAUDRATE_TABLE \ 180 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 181 182 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 183 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 184 185 /* Use the HUSH parser */ 186 #define CFG_HUSH_PARSER 187 #ifdef CFG_HUSH_PARSER 188 #define CFG_PROMPT_HUSH_PS2 "> " 189 #endif 190 191 /* I2C */ 192 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 193 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 194 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 195 #define CFG_I2C_SLAVE 0x7F 196 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 197 198 /* General PCI */ 199 #define CFG_PCI_MEM_BASE 0xe0000000 200 #define CFG_PCI_MEM_PHYS 0xe0000000 201 #define CFG_PCI_MEM_SIZE 0x10000000 202 #if defined(CONFIG_PCI) 203 #define CONFIG_NET_MULTI 204 #undef CONFIG_EEPRO100 205 #define CONFIG_TULIP 206 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 207 #if !defined(CONFIG_PCI_PNP) 208 #define PCI_ENET0_IOADDR 0xe0000000 209 #define PCI_ENET0_MEMADDR 0xe0000000 210 #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ 211 #endif 212 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 213 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 214 #if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 8 */ 215 #define CFG_PCI_SUBSYS_DEVICEID 0x0003 216 #else 217 #define CFG_PCI_SUBSYS_DEVICEID 0x0008 218 #endif 219 #elif defined(CONFIG_TSEC_ENET) 220 #define CONFIG_NET_MULTI 1 221 #define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ 222 #define CONFIG_MII 1 /* MII PHY management */ 223 #define CONFIG_PHY_ADDR 8 /* PHY address */ 224 #endif 225 226 /* Environment */ 227 #ifndef CFG_RAMBOOT 228 #if defined(CONFIG_RAM_AS_FLASH) 229 #define CFG_ENV_IS_NOWHERE 230 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) 231 #define CFG_ENV_SIZE 0x2000 232 #else 233 #define CFG_ENV_IS_IN_FLASH 1 234 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 235 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 236 #endif 237 #define CFG_ENV_SIZE 0x2000 238 #else 239 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 240 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 241 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 242 #define CFG_ENV_SIZE 0x2000 243 #endif 244 245 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200" 246 /*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ 247 #define CONFIG_BOOTCOMMAND "bootm 0xff300000 0xff700000" 248 #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ 249 250 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 251 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 252 253 #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) 254 #if defined(CONFIG_PCI) 255 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_PCI | CFG_CMD_I2C ) & \ 256 ~(CFG_CMD_ENV | CFG_CMD_LOADS )) 257 #else 258 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) & \ 259 ~(CFG_CMD_ENV | \ 260 CFG_CMD_LOADS )) 261 #endif 262 #else 263 #if defined(CONFIG_PCI) 264 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_PING | CFG_CMD_I2C ) 265 #else 266 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) 267 #endif 268 #endif 269 #include <cmd_confdefs.h> 270 271 #undef CONFIG_WATCHDOG /* watchdog disabled */ 272 273 /* 274 * Miscellaneous configurable options 275 */ 276 #define CFG_LONGHELP /* undef to save memory */ 277 #define CFG_PROMPT "MPC8540ADS=> " /* Monitor Command Prompt */ 278 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 279 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 280 #else 281 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 282 #endif 283 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 284 #define CFG_MAXARGS 16 /* max number of command args */ 285 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 286 #define CFG_LOAD_ADDR 0x1000000 /* default load address */ 287 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ 288 289 /* 290 * For booting Linux, the board info and command line data 291 * have to be in the first 8 MB of memory, since this is 292 * the maximum mapped by the Linux kernel during initialization. 293 */ 294 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 295 296 /* Cache Configuration */ 297 #define CFG_DCACHE_SIZE 32768 298 #define CFG_CACHELINE_SIZE 32 299 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 300 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 301 #endif 302 303 /* 304 * Internal Definitions 305 * 306 * Boot Flags 307 */ 308 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 309 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 310 311 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 312 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 313 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 314 #endif 315 316 /* NOTE: change below for your network setting!!! */ 317 #if defined(CONFIG_TSEC_ENET) 318 #define CONFIG_ETHADDR 00:01:af:07:9b:8a 319 #define CONFIG_ETH1ADDR 00:01:af:07:9b:8b 320 #define CONFIG_ETH2ADDR 00:01:af:07:9b:8c 321 #endif 322 323 #define CONFIG_SERVERIP 163.12.64.52 324 #define CONFIG_IPADDR 10.82.0.105 325 #define CONFIG_GATEWAYIP 10.82.1.254 326 #define CONFIG_NETMASK 255.255.254.0 327 #define CONFIG_HOSTNAME MPC8560ADS_PILOT_003 328 #define CONFIG_ROOTPATH /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx 329 #define CONFIG_BOOTFILE pImage 330 331 #endif /* __CONFIG_H */ 332