1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8540ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 42 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 43 44 #ifndef CONFIG_HAS_FEC 45 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 46 #endif 47 48 #define CONFIG_PCI 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 52 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 53 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 54 55 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 56 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 57 58 59 /* 60 * sysclk for MPC85xx 61 * 62 * Two valid values are: 63 * 33000000 64 * 66000000 65 * 66 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 67 * is likely the desired value here, so that is now the default. 68 * The board, however, can run at 66MHz. In any event, this value 69 * must match the settings of some switches. Details can be found 70 * in the README.mpc85xxads. 71 */ 72 73 #ifndef CONFIG_SYS_CLK_FREQ 74 #define CONFIG_SYS_CLK_FREQ 33000000 75 #endif 76 77 78 /* 79 * These can be toggled for performance analysis, otherwise use default. 80 */ 81 #define CONFIG_L2_CACHE /* toggle L2 cache */ 82 #define CONFIG_BTB /* toggle branch predition */ 83 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 84 85 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 86 87 #undef CFG_DRAM_TEST /* memory test, takes time */ 88 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 89 #define CFG_MEMTEST_END 0x00400000 90 91 92 /* 93 * Base addresses -- Note these are effective addresses where the 94 * actual resources get mapped (not physical addresses) 95 */ 96 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 97 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 98 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 99 100 101 /* 102 * DDR Setup 103 */ 104 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 105 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 106 107 #if defined(CONFIG_SPD_EEPROM) 108 /* 109 * Determine DDR configuration from I2C interface. 110 */ 111 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 112 113 #else 114 /* 115 * Manually set up DDR parameters 116 */ 117 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 118 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 119 #define CFG_DDR_CS0_CONFIG 0x80000002 120 #define CFG_DDR_TIMING_1 0x37344321 121 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 122 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 123 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 124 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 125 #endif 126 127 128 /* 129 * SDRAM on the Local Bus 130 */ 131 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 132 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 133 134 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 135 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 136 137 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 138 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 139 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 140 #undef CFG_FLASH_CHECKSUM 141 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 142 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 143 144 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 145 146 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 147 #define CFG_RAMBOOT 148 #else 149 #undef CFG_RAMBOOT 150 #endif 151 152 #define CFG_FLASH_CFI_DRIVER 153 #define CFG_FLASH_CFI 154 #define CFG_FLASH_EMPTY_INFO 155 156 #undef CONFIG_CLOCKS_IN_MHZ 157 158 159 /* 160 * Local Bus Definitions 161 */ 162 163 /* 164 * Base Register 2 and Option Register 2 configure SDRAM. 165 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 166 * 167 * For BR2, need: 168 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 169 * port-size = 32-bits = BR2[19:20] = 11 170 * no parity checking = BR2[21:22] = 00 171 * SDRAM for MSEL = BR2[24:26] = 011 172 * Valid = BR[31] = 1 173 * 174 * 0 4 8 12 16 20 24 28 175 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 176 * 177 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 178 * FIXME: the top 17 bits of BR2. 179 */ 180 181 #define CFG_BR2_PRELIM 0xf0001861 182 183 /* 184 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 185 * 186 * For OR2, need: 187 * 64MB mask for AM, OR2[0:7] = 1111 1100 188 * XAM, OR2[17:18] = 11 189 * 9 columns OR2[19-21] = 010 190 * 13 rows OR2[23-25] = 100 191 * EAD set for extra time OR[31] = 1 192 * 193 * 0 4 8 12 16 20 24 28 194 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 195 */ 196 197 #define CFG_OR2_PRELIM 0xfc006901 198 199 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 200 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 201 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 202 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 203 204 /* 205 * LSDMR masks 206 */ 207 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 208 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 209 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 210 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 211 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 212 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 213 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 214 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 215 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 216 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 217 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 218 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 219 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 220 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 221 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 222 223 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 224 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 225 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 230 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 231 232 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 233 | CFG_LBC_LSDMR_RFCR5 \ 234 | CFG_LBC_LSDMR_PRETOACT3 \ 235 | CFG_LBC_LSDMR_ACTTORW3 \ 236 | CFG_LBC_LSDMR_BL8 \ 237 | CFG_LBC_LSDMR_WRC2 \ 238 | CFG_LBC_LSDMR_CL3 \ 239 | CFG_LBC_LSDMR_RFEN \ 240 ) 241 242 /* 243 * SDRAM Controller configuration sequence. 244 */ 245 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 246 | CFG_LBC_LSDMR_OP_PCHALL) 247 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 248 | CFG_LBC_LSDMR_OP_ARFRSH) 249 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 250 | CFG_LBC_LSDMR_OP_ARFRSH) 251 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 252 | CFG_LBC_LSDMR_OP_MRW) 253 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 254 | CFG_LBC_LSDMR_OP_NORMAL) 255 256 257 /* 258 * 32KB, 8-bit wide for ADS config reg 259 */ 260 #define CFG_BR4_PRELIM 0xf8000801 261 #define CFG_OR4_PRELIM 0xffffe1f1 262 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 263 264 #define CONFIG_L1_INIT_RAM 265 #define CFG_INIT_RAM_LOCK 1 266 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 267 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 268 269 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 270 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 271 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 272 273 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 274 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 275 276 /* Serial Port */ 277 #define CONFIG_CONS_INDEX 1 278 #undef CONFIG_SERIAL_SOFTWARE_FIFO 279 #define CFG_NS16550 280 #define CFG_NS16550_SERIAL 281 #define CFG_NS16550_REG_SIZE 1 282 #define CFG_NS16550_CLK get_bus_freq(0) 283 284 #define CFG_BAUDRATE_TABLE \ 285 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 286 287 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 288 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 289 290 /* Use the HUSH parser */ 291 #define CFG_HUSH_PARSER 292 #ifdef CFG_HUSH_PARSER 293 #define CFG_PROMPT_HUSH_PS2 "> " 294 #endif 295 296 /* I2C */ 297 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 298 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 299 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 300 #define CFG_I2C_SLAVE 0x7F 301 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 302 303 /* RapidIO MMU */ 304 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 305 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 306 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 307 308 /* 309 * General PCI 310 * Addresses are mapped 1-1. 311 */ 312 #define CFG_PCI1_MEM_BASE 0x80000000 313 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 314 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 315 #define CFG_PCI1_IO_BASE 0xe2000000 316 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 317 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 318 319 #if defined(CONFIG_PCI) 320 321 #define CONFIG_NET_MULTI 322 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 323 324 #undef CONFIG_EEPRO100 325 #undef CONFIG_TULIP 326 327 #if !defined(CONFIG_PCI_PNP) 328 #define PCI_ENET0_IOADDR 0xe0000000 329 #define PCI_ENET0_MEMADDR 0xe0000000 330 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 331 #endif 332 333 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 334 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 335 336 #endif /* CONFIG_PCI */ 337 338 339 #if defined(CONFIG_TSEC_ENET) 340 341 #ifndef CONFIG_NET_MULTI 342 #define CONFIG_NET_MULTI 1 343 #endif 344 345 #define CONFIG_MII 1 /* MII PHY management */ 346 #define CONFIG_MPC85XX_TSEC1 1 347 #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" 348 #define CONFIG_MPC85XX_TSEC2 1 349 #define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" 350 #define TSEC1_PHY_ADDR 0 351 #define TSEC2_PHY_ADDR 1 352 #define TSEC1_PHYIDX 0 353 #define TSEC2_PHYIDX 0 354 355 356 #if CONFIG_HAS_FEC 357 #define CONFIG_MPC85XX_FEC 1 358 #define CONFIG_MPC85XX_FEC_NAME "FEC" 359 #define FEC_PHY_ADDR 3 360 #define FEC_PHYIDX 0 361 #endif 362 363 /* Options are: TSEC[0-1], FEC */ 364 #define CONFIG_ETHPRIME "TSEC0" 365 366 #endif /* CONFIG_TSEC_ENET */ 367 368 369 /* 370 * Environment 371 */ 372 #ifndef CFG_RAMBOOT 373 #define CFG_ENV_IS_IN_FLASH 1 374 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 375 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 376 #define CFG_ENV_SIZE 0x2000 377 #else 378 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 379 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 380 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 381 #define CFG_ENV_SIZE 0x2000 382 #endif 383 384 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 385 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 386 387 #if defined(CFG_RAMBOOT) 388 #if defined(CONFIG_PCI) 389 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 390 | CFG_CMD_PING \ 391 | CFG_CMD_PCI \ 392 | CFG_CMD_I2C) \ 393 & \ 394 ~(CFG_CMD_ENV \ 395 | CFG_CMD_LOADS)) 396 #else 397 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 398 | CFG_CMD_PING \ 399 | CFG_CMD_I2C) \ 400 & \ 401 ~(CFG_CMD_ENV \ 402 | CFG_CMD_LOADS)) 403 #endif 404 #else 405 #if defined(CONFIG_PCI) 406 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 407 | CFG_CMD_PCI \ 408 | CFG_CMD_PING \ 409 | CFG_CMD_I2C) 410 #else 411 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 412 | CFG_CMD_PING \ 413 | CFG_CMD_I2C) 414 #endif 415 #endif 416 417 #include <cmd_confdefs.h> 418 419 #undef CONFIG_WATCHDOG /* watchdog disabled */ 420 421 /* 422 * Miscellaneous configurable options 423 */ 424 #define CFG_LONGHELP /* undef to save memory */ 425 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 426 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 427 428 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 429 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 430 #else 431 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 432 #endif 433 434 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 435 #define CFG_MAXARGS 16 /* max number of command args */ 436 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 437 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 438 439 /* 440 * For booting Linux, the board info and command line data 441 * have to be in the first 8 MB of memory, since this is 442 * the maximum mapped by the Linux kernel during initialization. 443 */ 444 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 445 446 /* Cache Configuration */ 447 #define CFG_DCACHE_SIZE 32768 448 #define CFG_CACHELINE_SIZE 32 449 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 450 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 451 #endif 452 453 /* 454 * Internal Definitions 455 * 456 * Boot Flags 457 */ 458 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 459 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 460 461 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 462 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 463 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 464 #endif 465 466 467 /* 468 * Environment Configuration 469 */ 470 471 /* The mac addresses for all ethernet interface */ 472 #if defined(CONFIG_TSEC_ENET) 473 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 474 #define CONFIG_HAS_ETH1 475 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 476 #define CONFIG_HAS_ETH2 477 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 478 #endif 479 480 #define CONFIG_IPADDR 192.168.1.253 481 482 #define CONFIG_HOSTNAME unknown 483 #define CONFIG_ROOTPATH /nfsroot 484 #define CONFIG_BOOTFILE your.uImage 485 486 #define CONFIG_SERVERIP 192.168.1.1 487 #define CONFIG_GATEWAYIP 192.168.1.1 488 #define CONFIG_NETMASK 255.255.255.0 489 490 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 491 492 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 493 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 494 495 #define CONFIG_BAUDRATE 115200 496 497 #define CONFIG_EXTRA_ENV_SETTINGS \ 498 "netdev=eth0\0" \ 499 "consoledev=ttyS0\0" \ 500 "ramdiskaddr=400000\0" \ 501 "ramdiskfile=your.ramdisk.u-boot\0" 502 503 #define CONFIG_NFSBOOTCOMMAND \ 504 "setenv bootargs root=/dev/nfs rw " \ 505 "nfsroot=$serverip:$rootpath " \ 506 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 507 "console=$consoledev,$baudrate $othbootargs;" \ 508 "tftp $loadaddr $bootfile;" \ 509 "bootm $loadaddr" 510 511 #define CONFIG_RAMBOOTCOMMAND \ 512 "setenv bootargs root=/dev/ram rw " \ 513 "console=$consoledev,$baudrate $othbootargs;" \ 514 "tftp $ramdiskaddr $ramdiskfile;" \ 515 "tftp $loadaddr $bootfile;" \ 516 "bootm $loadaddr $ramdiskaddr" 517 518 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 519 520 #endif /* __CONFIG_H */ 521