1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8540ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 #define CONFIG_DISPLAY_BOARDINFO 22 23 /* High Level Configuration Options */ 24 #define CONFIG_BOOKE 1 /* BOOKE */ 25 #define CONFIG_E500 1 /* BOOKE e500 family */ 26 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 27 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 28 29 /* 30 * default CCARBAR is at 0xff700000 31 * assume U-Boot is less than 0.5MB 32 */ 33 #define CONFIG_SYS_TEXT_BASE 0xfff80000 34 35 #ifndef CONFIG_HAS_FEC 36 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 37 #endif 38 39 #define CONFIG_PCI 40 #define CONFIG_PCI_INDIRECT_BRIDGE 41 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 42 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 43 #define CONFIG_ENV_OVERWRITE 44 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 45 46 /* 47 * sysclk for MPC85xx 48 * 49 * Two valid values are: 50 * 33000000 51 * 66000000 52 * 53 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 54 * is likely the desired value here, so that is now the default. 55 * The board, however, can run at 66MHz. In any event, this value 56 * must match the settings of some switches. Details can be found 57 * in the README.mpc85xxads. 58 * 59 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 60 * 33MHz to accommodate, based on a PCI pin. 61 * Note that PCI-X won't work at 33MHz. 62 */ 63 64 #ifndef CONFIG_SYS_CLK_FREQ 65 #define CONFIG_SYS_CLK_FREQ 33000000 66 #endif 67 68 69 /* 70 * These can be toggled for performance analysis, otherwise use default. 71 */ 72 #define CONFIG_L2_CACHE /* toggle L2 cache */ 73 #define CONFIG_BTB /* toggle branch predition */ 74 75 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 76 #define CONFIG_SYS_MEMTEST_END 0x00400000 77 78 #define CONFIG_SYS_CCSRBAR 0xe0000000 79 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 80 81 /* DDR Setup */ 82 #define CONFIG_SYS_FSL_DDR1 83 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 84 #define CONFIG_DDR_SPD 85 #undef CONFIG_FSL_DDR_INTERACTIVE 86 87 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 88 89 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 90 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 91 92 #define CONFIG_NUM_DDR_CONTROLLERS 1 93 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 94 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 95 96 /* I2C addresses of SPD EEPROMs */ 97 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 98 99 /* These are used when DDR doesn't use SPD. */ 100 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 101 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 102 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 103 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 104 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 105 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 106 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 107 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 108 109 /* 110 * SDRAM on the Local Bus 111 */ 112 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 113 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 114 115 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 116 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 117 118 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 119 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 120 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 121 #undef CONFIG_SYS_FLASH_CHECKSUM 122 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 123 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 124 125 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 126 127 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 128 #define CONFIG_SYS_RAMBOOT 129 #else 130 #undef CONFIG_SYS_RAMBOOT 131 #endif 132 133 #define CONFIG_FLASH_CFI_DRIVER 134 #define CONFIG_SYS_FLASH_CFI 135 #define CONFIG_SYS_FLASH_EMPTY_INFO 136 137 #undef CONFIG_CLOCKS_IN_MHZ 138 139 140 /* 141 * Local Bus Definitions 142 */ 143 144 /* 145 * Base Register 2 and Option Register 2 configure SDRAM. 146 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 147 * 148 * For BR2, need: 149 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 150 * port-size = 32-bits = BR2[19:20] = 11 151 * no parity checking = BR2[21:22] = 00 152 * SDRAM for MSEL = BR2[24:26] = 011 153 * Valid = BR[31] = 1 154 * 155 * 0 4 8 12 16 20 24 28 156 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 157 * 158 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 159 * FIXME: the top 17 bits of BR2. 160 */ 161 162 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 163 164 /* 165 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 166 * 167 * For OR2, need: 168 * 64MB mask for AM, OR2[0:7] = 1111 1100 169 * XAM, OR2[17:18] = 11 170 * 9 columns OR2[19-21] = 010 171 * 13 rows OR2[23-25] = 100 172 * EAD set for extra time OR[31] = 1 173 * 174 * 0 4 8 12 16 20 24 28 175 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 176 */ 177 178 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 179 180 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 181 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 182 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 183 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 184 185 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 186 | LSDMR_RFCR5 \ 187 | LSDMR_PRETOACT3 \ 188 | LSDMR_ACTTORW3 \ 189 | LSDMR_BL8 \ 190 | LSDMR_WRC2 \ 191 | LSDMR_CL3 \ 192 | LSDMR_RFEN \ 193 ) 194 195 /* 196 * SDRAM Controller configuration sequence. 197 */ 198 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 199 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 200 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 201 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 202 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 203 204 205 /* 206 * 32KB, 8-bit wide for ADS config reg 207 */ 208 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 209 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 210 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 211 212 #define CONFIG_SYS_INIT_RAM_LOCK 1 213 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 214 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 215 216 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 217 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 218 219 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 220 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 221 222 /* Serial Port */ 223 #define CONFIG_CONS_INDEX 1 224 #define CONFIG_SYS_NS16550_SERIAL 225 #define CONFIG_SYS_NS16550_REG_SIZE 1 226 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 227 228 #define CONFIG_SYS_BAUDRATE_TABLE \ 229 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 230 231 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 232 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 233 234 /* Use the HUSH parser */ 235 #define CONFIG_SYS_HUSH_PARSER 236 #ifdef CONFIG_SYS_HUSH_PARSER 237 #endif 238 239 /* 240 * I2C 241 */ 242 #define CONFIG_SYS_I2C 243 #define CONFIG_SYS_I2C_FSL 244 #define CONFIG_SYS_FSL_I2C_SPEED 400000 245 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 246 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 247 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 248 249 /* RapidIO MMU */ 250 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 251 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 252 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 253 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 254 255 /* 256 * General PCI 257 * Memory space is mapped 1-1, but I/O space must start from 0. 258 */ 259 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 260 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 261 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 262 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 263 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 264 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 265 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 266 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 267 268 #if defined(CONFIG_PCI) 269 270 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 271 272 #undef CONFIG_EEPRO100 273 #undef CONFIG_TULIP 274 275 #if !defined(CONFIG_PCI_PNP) 276 #define PCI_ENET0_IOADDR 0xe0000000 277 #define PCI_ENET0_MEMADDR 0xe0000000 278 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 279 #endif 280 281 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 282 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 283 284 #endif /* CONFIG_PCI */ 285 286 287 #if defined(CONFIG_TSEC_ENET) 288 289 #define CONFIG_MII 1 /* MII PHY management */ 290 #define CONFIG_TSEC1 1 291 #define CONFIG_TSEC1_NAME "TSEC0" 292 #define CONFIG_TSEC2 1 293 #define CONFIG_TSEC2_NAME "TSEC1" 294 #define TSEC1_PHY_ADDR 0 295 #define TSEC2_PHY_ADDR 1 296 #define TSEC1_PHYIDX 0 297 #define TSEC2_PHYIDX 0 298 #define TSEC1_FLAGS TSEC_GIGABIT 299 #define TSEC2_FLAGS TSEC_GIGABIT 300 301 302 #if CONFIG_HAS_FEC 303 #define CONFIG_MPC85XX_FEC 1 304 #define CONFIG_MPC85XX_FEC_NAME "FEC" 305 #define FEC_PHY_ADDR 3 306 #define FEC_PHYIDX 0 307 #define FEC_FLAGS 0 308 #endif 309 310 /* Options are: TSEC[0-1], FEC */ 311 #define CONFIG_ETHPRIME "TSEC0" 312 313 #endif /* CONFIG_TSEC_ENET */ 314 315 316 /* 317 * Environment 318 */ 319 #ifndef CONFIG_SYS_RAMBOOT 320 #define CONFIG_ENV_IS_IN_FLASH 1 321 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 322 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 323 #define CONFIG_ENV_SIZE 0x2000 324 #else 325 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 326 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 327 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 328 #define CONFIG_ENV_SIZE 0x2000 329 #endif 330 331 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 332 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 333 334 335 /* 336 * BOOTP options 337 */ 338 #define CONFIG_BOOTP_BOOTFILESIZE 339 #define CONFIG_BOOTP_BOOTPATH 340 #define CONFIG_BOOTP_GATEWAY 341 #define CONFIG_BOOTP_HOSTNAME 342 343 344 /* 345 * Command line configuration. 346 */ 347 #define CONFIG_CMD_PING 348 #define CONFIG_CMD_I2C 349 #define CONFIG_CMD_IRQ 350 351 #if defined(CONFIG_PCI) 352 #define CONFIG_CMD_PCI 353 #endif 354 355 #undef CONFIG_WATCHDOG /* watchdog disabled */ 356 357 /* 358 * Miscellaneous configurable options 359 */ 360 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 361 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 362 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 363 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 364 365 #if defined(CONFIG_CMD_KGDB) 366 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 367 #else 368 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 369 #endif 370 371 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 372 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 373 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 374 375 /* 376 * For booting Linux, the board info and command line data 377 * have to be in the first 64 MB of memory, since this is 378 * the maximum mapped by the Linux kernel during initialization. 379 */ 380 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 381 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 382 383 #if defined(CONFIG_CMD_KGDB) 384 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 385 #endif 386 387 388 /* 389 * Environment Configuration 390 */ 391 392 /* The mac addresses for all ethernet interface */ 393 #if defined(CONFIG_TSEC_ENET) 394 #define CONFIG_HAS_ETH0 395 #define CONFIG_HAS_ETH1 396 #define CONFIG_HAS_ETH2 397 #endif 398 399 #define CONFIG_IPADDR 192.168.1.253 400 401 #define CONFIG_HOSTNAME unknown 402 #define CONFIG_ROOTPATH "/nfsroot" 403 #define CONFIG_BOOTFILE "your.uImage" 404 405 #define CONFIG_SERVERIP 192.168.1.1 406 #define CONFIG_GATEWAYIP 192.168.1.1 407 #define CONFIG_NETMASK 255.255.255.0 408 409 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 410 411 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 412 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 413 414 #define CONFIG_BAUDRATE 115200 415 416 #define CONFIG_EXTRA_ENV_SETTINGS \ 417 "netdev=eth0\0" \ 418 "consoledev=ttyS0\0" \ 419 "ramdiskaddr=1000000\0" \ 420 "ramdiskfile=your.ramdisk.u-boot\0" \ 421 "fdtaddr=400000\0" \ 422 "fdtfile=your.fdt.dtb\0" 423 424 #define CONFIG_NFSBOOTCOMMAND \ 425 "setenv bootargs root=/dev/nfs rw " \ 426 "nfsroot=$serverip:$rootpath " \ 427 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 428 "console=$consoledev,$baudrate $othbootargs;" \ 429 "tftp $loadaddr $bootfile;" \ 430 "tftp $fdtaddr $fdtfile;" \ 431 "bootm $loadaddr - $fdtaddr" 432 433 #define CONFIG_RAMBOOTCOMMAND \ 434 "setenv bootargs root=/dev/ram rw " \ 435 "console=$consoledev,$baudrate $othbootargs;" \ 436 "tftp $ramdiskaddr $ramdiskfile;" \ 437 "tftp $loadaddr $bootfile;" \ 438 "tftp $fdtaddr $fdtfile;" \ 439 "bootm $loadaddr $ramdiskaddr $fdtaddr" 440 441 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 442 443 #endif /* __CONFIG_H */ 444