1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8540ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 42 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 43 44 #ifndef CONFIG_HAS_FEC 45 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 46 #endif 47 48 #define CONFIG_PCI 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 52 53 /* 54 * sysclk for MPC85xx 55 * 56 * Two valid values are: 57 * 33000000 58 * 66000000 59 * 60 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 61 * is likely the desired value here, so that is now the default. 62 * The board, however, can run at 66MHz. In any event, this value 63 * must match the settings of some switches. Details can be found 64 * in the README.mpc85xxads. 65 * 66 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 67 * 33MHz to accommodate, based on a PCI pin. 68 * Note that PCI-X won't work at 33MHz. 69 */ 70 71 #ifndef CONFIG_SYS_CLK_FREQ 72 #define CONFIG_SYS_CLK_FREQ 33000000 73 #endif 74 75 76 /* 77 * These can be toggled for performance analysis, otherwise use default. 78 */ 79 #define CONFIG_L2_CACHE /* toggle L2 cache */ 80 #define CONFIG_BTB /* toggle branch predition */ 81 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 82 83 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 84 #define CFG_MEMTEST_END 0x00400000 85 86 87 /* 88 * Base addresses -- Note these are effective addresses where the 89 * actual resources get mapped (not physical addresses) 90 */ 91 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 92 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 93 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 94 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 95 96 /* DDR Setup */ 97 #define CONFIG_FSL_DDR1 98 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 99 #define CONFIG_DDR_SPD 100 #undef CONFIG_FSL_DDR_INTERACTIVE 101 102 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 103 104 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 105 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 110 111 /* I2C addresses of SPD EEPROMs */ 112 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 113 114 /* These are used when DDR doesn't use SPD. */ 115 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 116 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 117 #define CFG_DDR_CS0_CONFIG 0x80000002 118 #define CFG_DDR_TIMING_1 0x37344321 119 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 120 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 121 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 122 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 123 124 /* 125 * SDRAM on the Local Bus 126 */ 127 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 128 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 129 130 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 131 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 132 133 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 134 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 135 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 136 #undef CFG_FLASH_CHECKSUM 137 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 138 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 139 140 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 141 142 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 143 #define CFG_RAMBOOT 144 #else 145 #undef CFG_RAMBOOT 146 #endif 147 148 #define CONFIG_FLASH_CFI_DRIVER 149 #define CFG_FLASH_CFI 150 #define CFG_FLASH_EMPTY_INFO 151 152 #undef CONFIG_CLOCKS_IN_MHZ 153 154 155 /* 156 * Local Bus Definitions 157 */ 158 159 /* 160 * Base Register 2 and Option Register 2 configure SDRAM. 161 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 162 * 163 * For BR2, need: 164 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 165 * port-size = 32-bits = BR2[19:20] = 11 166 * no parity checking = BR2[21:22] = 00 167 * SDRAM for MSEL = BR2[24:26] = 011 168 * Valid = BR[31] = 1 169 * 170 * 0 4 8 12 16 20 24 28 171 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 172 * 173 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 174 * FIXME: the top 17 bits of BR2. 175 */ 176 177 #define CFG_BR2_PRELIM 0xf0001861 178 179 /* 180 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 181 * 182 * For OR2, need: 183 * 64MB mask for AM, OR2[0:7] = 1111 1100 184 * XAM, OR2[17:18] = 11 185 * 9 columns OR2[19-21] = 010 186 * 13 rows OR2[23-25] = 100 187 * EAD set for extra time OR[31] = 1 188 * 189 * 0 4 8 12 16 20 24 28 190 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 191 */ 192 193 #define CFG_OR2_PRELIM 0xfc006901 194 195 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 196 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 197 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 198 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 199 200 /* 201 * LSDMR masks 202 */ 203 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 204 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 205 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 206 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 207 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 208 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 209 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 210 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 211 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 212 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 213 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 214 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 215 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 216 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 217 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 218 219 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 220 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 221 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 222 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 223 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 224 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 225 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 227 228 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 229 | CFG_LBC_LSDMR_RFCR5 \ 230 | CFG_LBC_LSDMR_PRETOACT3 \ 231 | CFG_LBC_LSDMR_ACTTORW3 \ 232 | CFG_LBC_LSDMR_BL8 \ 233 | CFG_LBC_LSDMR_WRC2 \ 234 | CFG_LBC_LSDMR_CL3 \ 235 | CFG_LBC_LSDMR_RFEN \ 236 ) 237 238 /* 239 * SDRAM Controller configuration sequence. 240 */ 241 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 242 | CFG_LBC_LSDMR_OP_PCHALL) 243 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 244 | CFG_LBC_LSDMR_OP_ARFRSH) 245 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 246 | CFG_LBC_LSDMR_OP_ARFRSH) 247 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 248 | CFG_LBC_LSDMR_OP_MRW) 249 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 250 | CFG_LBC_LSDMR_OP_NORMAL) 251 252 253 /* 254 * 32KB, 8-bit wide for ADS config reg 255 */ 256 #define CFG_BR4_PRELIM 0xf8000801 257 #define CFG_OR4_PRELIM 0xffffe1f1 258 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 259 260 #define CONFIG_L1_INIT_RAM 261 #define CFG_INIT_RAM_LOCK 1 262 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 263 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 264 265 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 266 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 267 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 268 269 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 270 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 271 272 /* Serial Port */ 273 #define CONFIG_CONS_INDEX 1 274 #undef CONFIG_SERIAL_SOFTWARE_FIFO 275 #define CFG_NS16550 276 #define CFG_NS16550_SERIAL 277 #define CFG_NS16550_REG_SIZE 1 278 #define CFG_NS16550_CLK get_bus_freq(0) 279 280 #define CFG_BAUDRATE_TABLE \ 281 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 282 283 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 284 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 285 286 /* Use the HUSH parser */ 287 #define CFG_HUSH_PARSER 288 #ifdef CFG_HUSH_PARSER 289 #define CFG_PROMPT_HUSH_PS2 "> " 290 #endif 291 292 /* pass open firmware flat tree */ 293 #define CONFIG_OF_LIBFDT 1 294 #define CONFIG_OF_BOARD_SETUP 1 295 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 296 297 #define CFG_64BIT_VSPRINTF 1 298 #define CFG_64BIT_STRTOUL 1 299 300 /* 301 * I2C 302 */ 303 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 304 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 305 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 306 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 307 #define CFG_I2C_SLAVE 0x7F 308 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 309 #define CFG_I2C_OFFSET 0x3000 310 311 /* RapidIO MMU */ 312 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 313 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 314 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 315 316 /* 317 * General PCI 318 * Memory space is mapped 1-1, but I/O space must start from 0. 319 */ 320 #define CFG_PCI1_MEM_BASE 0x80000000 321 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 322 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 323 #define CFG_PCI1_IO_BASE 0x00000000 324 #define CFG_PCI1_IO_PHYS 0xe2000000 325 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ 326 327 #if defined(CONFIG_PCI) 328 329 #define CONFIG_NET_MULTI 330 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 331 332 #undef CONFIG_EEPRO100 333 #undef CONFIG_TULIP 334 335 #if !defined(CONFIG_PCI_PNP) 336 #define PCI_ENET0_IOADDR 0xe0000000 337 #define PCI_ENET0_MEMADDR 0xe0000000 338 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 339 #endif 340 341 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 342 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 343 344 #endif /* CONFIG_PCI */ 345 346 347 #if defined(CONFIG_TSEC_ENET) 348 349 #ifndef CONFIG_NET_MULTI 350 #define CONFIG_NET_MULTI 1 351 #endif 352 353 #define CONFIG_MII 1 /* MII PHY management */ 354 #define CONFIG_TSEC1 1 355 #define CONFIG_TSEC1_NAME "TSEC0" 356 #define CONFIG_TSEC2 1 357 #define CONFIG_TSEC2_NAME "TSEC1" 358 #define TSEC1_PHY_ADDR 0 359 #define TSEC2_PHY_ADDR 1 360 #define TSEC1_PHYIDX 0 361 #define TSEC2_PHYIDX 0 362 #define TSEC1_FLAGS TSEC_GIGABIT 363 #define TSEC2_FLAGS TSEC_GIGABIT 364 365 366 #if CONFIG_HAS_FEC 367 #define CONFIG_MPC85XX_FEC 1 368 #define CONFIG_MPC85XX_FEC_NAME "FEC" 369 #define FEC_PHY_ADDR 3 370 #define FEC_PHYIDX 0 371 #define FEC_FLAGS 0 372 #endif 373 374 /* Options are: TSEC[0-1], FEC */ 375 #define CONFIG_ETHPRIME "TSEC0" 376 377 #endif /* CONFIG_TSEC_ENET */ 378 379 380 /* 381 * Environment 382 */ 383 #ifndef CFG_RAMBOOT 384 #define CFG_ENV_IS_IN_FLASH 1 385 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 386 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 387 #define CFG_ENV_SIZE 0x2000 388 #else 389 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 390 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 391 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 392 #define CFG_ENV_SIZE 0x2000 393 #endif 394 395 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 396 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 397 398 399 /* 400 * BOOTP options 401 */ 402 #define CONFIG_BOOTP_BOOTFILESIZE 403 #define CONFIG_BOOTP_BOOTPATH 404 #define CONFIG_BOOTP_GATEWAY 405 #define CONFIG_BOOTP_HOSTNAME 406 407 408 /* 409 * Command line configuration. 410 */ 411 #include <config_cmd_default.h> 412 413 #define CONFIG_CMD_PING 414 #define CONFIG_CMD_I2C 415 #define CONFIG_CMD_ELF 416 417 #if defined(CONFIG_PCI) 418 #define CONFIG_CMD_PCI 419 #endif 420 421 #if defined(CFG_RAMBOOT) 422 #undef CONFIG_CMD_ENV 423 #undef CONFIG_CMD_LOADS 424 #endif 425 426 427 #undef CONFIG_WATCHDOG /* watchdog disabled */ 428 429 /* 430 * Miscellaneous configurable options 431 */ 432 #define CFG_LONGHELP /* undef to save memory */ 433 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 434 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 435 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 436 437 #if defined(CONFIG_CMD_KGDB) 438 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 439 #else 440 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 441 #endif 442 443 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 444 #define CFG_MAXARGS 16 /* max number of command args */ 445 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 446 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 447 448 /* 449 * For booting Linux, the board info and command line data 450 * have to be in the first 8 MB of memory, since this is 451 * the maximum mapped by the Linux kernel during initialization. 452 */ 453 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 454 455 /* 456 * Internal Definitions 457 * 458 * Boot Flags 459 */ 460 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 461 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 462 463 #if defined(CONFIG_CMD_KGDB) 464 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 465 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 466 #endif 467 468 469 /* 470 * Environment Configuration 471 */ 472 473 /* The mac addresses for all ethernet interface */ 474 #if defined(CONFIG_TSEC_ENET) 475 #define CONFIG_HAS_ETH0 476 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 477 #define CONFIG_HAS_ETH1 478 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 479 #define CONFIG_HAS_ETH2 480 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 481 #endif 482 483 #define CONFIG_IPADDR 192.168.1.253 484 485 #define CONFIG_HOSTNAME unknown 486 #define CONFIG_ROOTPATH /nfsroot 487 #define CONFIG_BOOTFILE your.uImage 488 489 #define CONFIG_SERVERIP 192.168.1.1 490 #define CONFIG_GATEWAYIP 192.168.1.1 491 #define CONFIG_NETMASK 255.255.255.0 492 493 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 494 495 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 496 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 497 498 #define CONFIG_BAUDRATE 115200 499 500 #define CONFIG_EXTRA_ENV_SETTINGS \ 501 "netdev=eth0\0" \ 502 "consoledev=ttyS0\0" \ 503 "ramdiskaddr=1000000\0" \ 504 "ramdiskfile=your.ramdisk.u-boot\0" \ 505 "fdtaddr=400000\0" \ 506 "fdtfile=your.fdt.dtb\0" 507 508 #define CONFIG_NFSBOOTCOMMAND \ 509 "setenv bootargs root=/dev/nfs rw " \ 510 "nfsroot=$serverip:$rootpath " \ 511 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 512 "console=$consoledev,$baudrate $othbootargs;" \ 513 "tftp $loadaddr $bootfile;" \ 514 "tftp $fdtaddr $fdtfile;" \ 515 "bootm $loadaddr - $fdtaddr" 516 517 #define CONFIG_RAMBOOTCOMMAND \ 518 "setenv bootargs root=/dev/ram rw " \ 519 "console=$consoledev,$baudrate $othbootargs;" \ 520 "tftp $ramdiskaddr $ramdiskfile;" \ 521 "tftp $loadaddr $bootfile;" \ 522 "tftp $fdtaddr $fdtfile;" \ 523 "bootm $loadaddr $ramdiskaddr $fdtaddr" 524 525 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 526 527 #endif /* __CONFIG_H */ 528