1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8540ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 42 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 43 44 #ifndef CONFIG_HAS_FEC 45 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 46 #endif 47 48 #define CONFIG_PCI 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 52 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 53 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 54 55 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 56 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 57 58 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 59 60 /* 61 * sysclk for MPC85xx 62 * 63 * Two valid values are: 64 * 33000000 65 * 66000000 66 * 67 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 68 * is likely the desired value here, so that is now the default. 69 * The board, however, can run at 66MHz. In any event, this value 70 * must match the settings of some switches. Details can be found 71 * in the README.mpc85xxads. 72 * 73 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 74 * 33MHz to accommodate, based on a PCI pin. 75 * Note that PCI-X won't work at 33MHz. 76 */ 77 78 #ifndef CONFIG_SYS_CLK_FREQ 79 #define CONFIG_SYS_CLK_FREQ 33000000 80 #endif 81 82 83 /* 84 * These can be toggled for performance analysis, otherwise use default. 85 */ 86 #define CONFIG_L2_CACHE /* toggle L2 cache */ 87 #define CONFIG_BTB /* toggle branch predition */ 88 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 89 90 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 91 #define CFG_MEMTEST_END 0x00400000 92 93 94 /* 95 * Base addresses -- Note these are effective addresses where the 96 * actual resources get mapped (not physical addresses) 97 */ 98 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 99 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 100 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 101 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 102 103 104 /* 105 * DDR Setup 106 */ 107 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 108 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 109 110 #if defined(CONFIG_SPD_EEPROM) 111 /* 112 * Determine DDR configuration from I2C interface. 113 */ 114 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 115 116 #else 117 /* 118 * Manually set up DDR parameters 119 */ 120 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 121 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 122 #define CFG_DDR_CS0_CONFIG 0x80000002 123 #define CFG_DDR_TIMING_1 0x37344321 124 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 125 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 126 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 127 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 128 #endif 129 130 131 /* 132 * SDRAM on the Local Bus 133 */ 134 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 135 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 136 137 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 138 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 139 140 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 141 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 142 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 143 #undef CFG_FLASH_CHECKSUM 144 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 145 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 146 147 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 148 149 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 150 #define CFG_RAMBOOT 151 #else 152 #undef CFG_RAMBOOT 153 #endif 154 155 #define CFG_FLASH_CFI_DRIVER 156 #define CFG_FLASH_CFI 157 #define CFG_FLASH_EMPTY_INFO 158 159 #undef CONFIG_CLOCKS_IN_MHZ 160 161 162 /* 163 * Local Bus Definitions 164 */ 165 166 /* 167 * Base Register 2 and Option Register 2 configure SDRAM. 168 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 169 * 170 * For BR2, need: 171 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 172 * port-size = 32-bits = BR2[19:20] = 11 173 * no parity checking = BR2[21:22] = 00 174 * SDRAM for MSEL = BR2[24:26] = 011 175 * Valid = BR[31] = 1 176 * 177 * 0 4 8 12 16 20 24 28 178 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 179 * 180 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 181 * FIXME: the top 17 bits of BR2. 182 */ 183 184 #define CFG_BR2_PRELIM 0xf0001861 185 186 /* 187 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 188 * 189 * For OR2, need: 190 * 64MB mask for AM, OR2[0:7] = 1111 1100 191 * XAM, OR2[17:18] = 11 192 * 9 columns OR2[19-21] = 010 193 * 13 rows OR2[23-25] = 100 194 * EAD set for extra time OR[31] = 1 195 * 196 * 0 4 8 12 16 20 24 28 197 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 198 */ 199 200 #define CFG_OR2_PRELIM 0xfc006901 201 202 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 203 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 204 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 205 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 206 207 /* 208 * LSDMR masks 209 */ 210 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 211 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 212 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 213 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 214 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 215 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 216 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 217 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 218 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 219 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 220 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 221 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 222 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 223 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 224 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 225 226 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 230 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 231 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 232 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 233 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 234 235 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 236 | CFG_LBC_LSDMR_RFCR5 \ 237 | CFG_LBC_LSDMR_PRETOACT3 \ 238 | CFG_LBC_LSDMR_ACTTORW3 \ 239 | CFG_LBC_LSDMR_BL8 \ 240 | CFG_LBC_LSDMR_WRC2 \ 241 | CFG_LBC_LSDMR_CL3 \ 242 | CFG_LBC_LSDMR_RFEN \ 243 ) 244 245 /* 246 * SDRAM Controller configuration sequence. 247 */ 248 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 249 | CFG_LBC_LSDMR_OP_PCHALL) 250 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 251 | CFG_LBC_LSDMR_OP_ARFRSH) 252 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 253 | CFG_LBC_LSDMR_OP_ARFRSH) 254 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 255 | CFG_LBC_LSDMR_OP_MRW) 256 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 257 | CFG_LBC_LSDMR_OP_NORMAL) 258 259 260 /* 261 * 32KB, 8-bit wide for ADS config reg 262 */ 263 #define CFG_BR4_PRELIM 0xf8000801 264 #define CFG_OR4_PRELIM 0xffffe1f1 265 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 266 267 #define CONFIG_L1_INIT_RAM 268 #define CFG_INIT_RAM_LOCK 1 269 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 270 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 271 272 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 273 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 274 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 275 276 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 277 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 278 279 /* Serial Port */ 280 #define CONFIG_CONS_INDEX 1 281 #undef CONFIG_SERIAL_SOFTWARE_FIFO 282 #define CFG_NS16550 283 #define CFG_NS16550_SERIAL 284 #define CFG_NS16550_REG_SIZE 1 285 #define CFG_NS16550_CLK get_bus_freq(0) 286 287 #define CFG_BAUDRATE_TABLE \ 288 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 289 290 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 291 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 292 293 /* Use the HUSH parser */ 294 #define CFG_HUSH_PARSER 295 #ifdef CFG_HUSH_PARSER 296 #define CFG_PROMPT_HUSH_PS2 "> " 297 #endif 298 299 /* pass open firmware flat tree */ 300 #define CONFIG_OF_LIBFDT 1 301 #define CONFIG_OF_BOARD_SETUP 1 302 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 303 304 #define CFG_64BIT_VSPRINTF 1 305 #define CFG_64BIT_STRTOUL 1 306 307 /* 308 * I2C 309 */ 310 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 311 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 312 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 313 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 314 #define CFG_I2C_SLAVE 0x7F 315 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 316 #define CFG_I2C_OFFSET 0x3000 317 318 /* RapidIO MMU */ 319 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 320 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 321 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 322 323 /* 324 * General PCI 325 * Memory space is mapped 1-1, but I/O space must start from 0. 326 */ 327 #define CFG_PCI1_MEM_BASE 0x80000000 328 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 329 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 330 #define CFG_PCI1_IO_BASE 0x00000000 331 #define CFG_PCI1_IO_PHYS 0xe2000000 332 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ 333 334 #if defined(CONFIG_PCI) 335 336 #define CONFIG_NET_MULTI 337 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 338 339 #undef CONFIG_EEPRO100 340 #undef CONFIG_TULIP 341 342 #if !defined(CONFIG_PCI_PNP) 343 #define PCI_ENET0_IOADDR 0xe0000000 344 #define PCI_ENET0_MEMADDR 0xe0000000 345 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 346 #endif 347 348 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 349 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 350 351 #endif /* CONFIG_PCI */ 352 353 354 #if defined(CONFIG_TSEC_ENET) 355 356 #ifndef CONFIG_NET_MULTI 357 #define CONFIG_NET_MULTI 1 358 #endif 359 360 #define CONFIG_MII 1 /* MII PHY management */ 361 #define CONFIG_TSEC1 1 362 #define CONFIG_TSEC1_NAME "TSEC0" 363 #define CONFIG_TSEC2 1 364 #define CONFIG_TSEC2_NAME "TSEC1" 365 #define TSEC1_PHY_ADDR 0 366 #define TSEC2_PHY_ADDR 1 367 #define TSEC1_PHYIDX 0 368 #define TSEC2_PHYIDX 0 369 #define TSEC1_FLAGS TSEC_GIGABIT 370 #define TSEC2_FLAGS TSEC_GIGABIT 371 372 373 #if CONFIG_HAS_FEC 374 #define CONFIG_MPC85XX_FEC 1 375 #define CONFIG_MPC85XX_FEC_NAME "FEC" 376 #define FEC_PHY_ADDR 3 377 #define FEC_PHYIDX 0 378 #define FEC_FLAGS 0 379 #endif 380 381 /* Options are: TSEC[0-1], FEC */ 382 #define CONFIG_ETHPRIME "TSEC0" 383 384 #endif /* CONFIG_TSEC_ENET */ 385 386 387 /* 388 * Environment 389 */ 390 #ifndef CFG_RAMBOOT 391 #define CFG_ENV_IS_IN_FLASH 1 392 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 393 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 394 #define CFG_ENV_SIZE 0x2000 395 #else 396 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 397 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 398 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 399 #define CFG_ENV_SIZE 0x2000 400 #endif 401 402 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 403 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 404 405 406 /* 407 * BOOTP options 408 */ 409 #define CONFIG_BOOTP_BOOTFILESIZE 410 #define CONFIG_BOOTP_BOOTPATH 411 #define CONFIG_BOOTP_GATEWAY 412 #define CONFIG_BOOTP_HOSTNAME 413 414 415 /* 416 * Command line configuration. 417 */ 418 #include <config_cmd_default.h> 419 420 #define CONFIG_CMD_PING 421 #define CONFIG_CMD_I2C 422 #define CONFIG_CMD_ELF 423 424 #if defined(CONFIG_PCI) 425 #define CONFIG_CMD_PCI 426 #endif 427 428 #if defined(CFG_RAMBOOT) 429 #undef CONFIG_CMD_ENV 430 #undef CONFIG_CMD_LOADS 431 #endif 432 433 434 #undef CONFIG_WATCHDOG /* watchdog disabled */ 435 436 /* 437 * Miscellaneous configurable options 438 */ 439 #define CFG_LONGHELP /* undef to save memory */ 440 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 441 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 442 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 443 444 #if defined(CONFIG_CMD_KGDB) 445 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 446 #else 447 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 448 #endif 449 450 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 451 #define CFG_MAXARGS 16 /* max number of command args */ 452 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 453 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 454 455 /* 456 * For booting Linux, the board info and command line data 457 * have to be in the first 8 MB of memory, since this is 458 * the maximum mapped by the Linux kernel during initialization. 459 */ 460 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 461 462 /* 463 * Internal Definitions 464 * 465 * Boot Flags 466 */ 467 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 468 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 469 470 #if defined(CONFIG_CMD_KGDB) 471 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 472 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 473 #endif 474 475 476 /* 477 * Environment Configuration 478 */ 479 480 /* The mac addresses for all ethernet interface */ 481 #if defined(CONFIG_TSEC_ENET) 482 #define CONFIG_HAS_ETH0 483 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 484 #define CONFIG_HAS_ETH1 485 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 486 #define CONFIG_HAS_ETH2 487 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 488 #endif 489 490 #define CONFIG_IPADDR 192.168.1.253 491 492 #define CONFIG_HOSTNAME unknown 493 #define CONFIG_ROOTPATH /nfsroot 494 #define CONFIG_BOOTFILE your.uImage 495 496 #define CONFIG_SERVERIP 192.168.1.1 497 #define CONFIG_GATEWAYIP 192.168.1.1 498 #define CONFIG_NETMASK 255.255.255.0 499 500 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 501 502 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 503 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 504 505 #define CONFIG_BAUDRATE 115200 506 507 #define CONFIG_EXTRA_ENV_SETTINGS \ 508 "netdev=eth0\0" \ 509 "consoledev=ttyS0\0" \ 510 "ramdiskaddr=1000000\0" \ 511 "ramdiskfile=your.ramdisk.u-boot\0" \ 512 "fdtaddr=400000\0" \ 513 "fdtfile=your.fdt.dtb\0" 514 515 #define CONFIG_NFSBOOTCOMMAND \ 516 "setenv bootargs root=/dev/nfs rw " \ 517 "nfsroot=$serverip:$rootpath " \ 518 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 519 "console=$consoledev,$baudrate $othbootargs;" \ 520 "tftp $loadaddr $bootfile;" \ 521 "tftp $fdtaddr $fdtfile;" \ 522 "bootm $loadaddr - $fdtaddr" 523 524 #define CONFIG_RAMBOOTCOMMAND \ 525 "setenv bootargs root=/dev/ram rw " \ 526 "console=$consoledev,$baudrate $othbootargs;" \ 527 "tftp $ramdiskaddr $ramdiskfile;" \ 528 "tftp $loadaddr $bootfile;" \ 529 "tftp $fdtaddr $fdtfile;" \ 530 "bootm $loadaddr $ramdiskaddr $fdtaddr" 531 532 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 533 534 #endif /* __CONFIG_H */ 535