1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8540ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 42 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 43 44 #ifndef CONFIG_HAS_FEC 45 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 46 #endif 47 48 #define CONFIG_PCI 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 52 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 53 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 54 55 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 56 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 57 58 59 /* 60 * sysclk for MPC85xx 61 * 62 * Two valid values are: 63 * 33000000 64 * 66000000 65 * 66 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 67 * is likely the desired value here, so that is now the default. 68 * The board, however, can run at 66MHz. In any event, this value 69 * must match the settings of some switches. Details can be found 70 * in the README.mpc85xxads. 71 * 72 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 73 * 33MHz to accommodate, based on a PCI pin. 74 * Note that PCI-X won't work at 33MHz. 75 */ 76 77 #ifndef CONFIG_SYS_CLK_FREQ 78 #define CONFIG_SYS_CLK_FREQ 33000000 79 #endif 80 81 82 /* 83 * These can be toggled for performance analysis, otherwise use default. 84 */ 85 #define CONFIG_L2_CACHE /* toggle L2 cache */ 86 #define CONFIG_BTB /* toggle branch predition */ 87 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 88 89 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 90 91 #undef CFG_DRAM_TEST /* memory test, takes time */ 92 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 93 #define CFG_MEMTEST_END 0x00400000 94 95 96 /* 97 * Base addresses -- Note these are effective addresses where the 98 * actual resources get mapped (not physical addresses) 99 */ 100 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 101 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 102 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 103 104 105 /* 106 * DDR Setup 107 */ 108 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 109 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 110 111 #if defined(CONFIG_SPD_EEPROM) 112 /* 113 * Determine DDR configuration from I2C interface. 114 */ 115 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 116 117 #else 118 /* 119 * Manually set up DDR parameters 120 */ 121 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 122 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 123 #define CFG_DDR_CS0_CONFIG 0x80000002 124 #define CFG_DDR_TIMING_1 0x37344321 125 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 126 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 127 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 128 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 129 #endif 130 131 132 /* 133 * SDRAM on the Local Bus 134 */ 135 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 136 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 137 138 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 139 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 140 141 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 142 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 143 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 144 #undef CFG_FLASH_CHECKSUM 145 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 146 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 147 148 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 149 150 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 151 #define CFG_RAMBOOT 152 #else 153 #undef CFG_RAMBOOT 154 #endif 155 156 #define CFG_FLASH_CFI_DRIVER 157 #define CFG_FLASH_CFI 158 #define CFG_FLASH_EMPTY_INFO 159 160 #undef CONFIG_CLOCKS_IN_MHZ 161 162 163 /* 164 * Local Bus Definitions 165 */ 166 167 /* 168 * Base Register 2 and Option Register 2 configure SDRAM. 169 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 170 * 171 * For BR2, need: 172 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 173 * port-size = 32-bits = BR2[19:20] = 11 174 * no parity checking = BR2[21:22] = 00 175 * SDRAM for MSEL = BR2[24:26] = 011 176 * Valid = BR[31] = 1 177 * 178 * 0 4 8 12 16 20 24 28 179 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 180 * 181 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 182 * FIXME: the top 17 bits of BR2. 183 */ 184 185 #define CFG_BR2_PRELIM 0xf0001861 186 187 /* 188 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 189 * 190 * For OR2, need: 191 * 64MB mask for AM, OR2[0:7] = 1111 1100 192 * XAM, OR2[17:18] = 11 193 * 9 columns OR2[19-21] = 010 194 * 13 rows OR2[23-25] = 100 195 * EAD set for extra time OR[31] = 1 196 * 197 * 0 4 8 12 16 20 24 28 198 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 199 */ 200 201 #define CFG_OR2_PRELIM 0xfc006901 202 203 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 204 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 205 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 206 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 207 208 /* 209 * LSDMR masks 210 */ 211 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 212 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 213 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 214 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 215 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 216 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 217 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 218 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 219 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 220 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 221 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 222 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 223 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 224 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 225 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 226 227 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 230 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 231 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 232 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 233 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 234 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 235 236 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 237 | CFG_LBC_LSDMR_RFCR5 \ 238 | CFG_LBC_LSDMR_PRETOACT3 \ 239 | CFG_LBC_LSDMR_ACTTORW3 \ 240 | CFG_LBC_LSDMR_BL8 \ 241 | CFG_LBC_LSDMR_WRC2 \ 242 | CFG_LBC_LSDMR_CL3 \ 243 | CFG_LBC_LSDMR_RFEN \ 244 ) 245 246 /* 247 * SDRAM Controller configuration sequence. 248 */ 249 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 250 | CFG_LBC_LSDMR_OP_PCHALL) 251 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 252 | CFG_LBC_LSDMR_OP_ARFRSH) 253 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 254 | CFG_LBC_LSDMR_OP_ARFRSH) 255 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 256 | CFG_LBC_LSDMR_OP_MRW) 257 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 258 | CFG_LBC_LSDMR_OP_NORMAL) 259 260 261 /* 262 * 32KB, 8-bit wide for ADS config reg 263 */ 264 #define CFG_BR4_PRELIM 0xf8000801 265 #define CFG_OR4_PRELIM 0xffffe1f1 266 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 267 268 #define CONFIG_L1_INIT_RAM 269 #define CFG_INIT_RAM_LOCK 1 270 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 271 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 272 273 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 274 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 275 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 276 277 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 278 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 279 280 /* Serial Port */ 281 #define CONFIG_CONS_INDEX 1 282 #undef CONFIG_SERIAL_SOFTWARE_FIFO 283 #define CFG_NS16550 284 #define CFG_NS16550_SERIAL 285 #define CFG_NS16550_REG_SIZE 1 286 #define CFG_NS16550_CLK get_bus_freq(0) 287 288 #define CFG_BAUDRATE_TABLE \ 289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 290 291 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 292 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 293 294 /* Use the HUSH parser */ 295 #define CFG_HUSH_PARSER 296 #ifdef CFG_HUSH_PARSER 297 #define CFG_PROMPT_HUSH_PS2 "> " 298 #endif 299 300 /* pass open firmware flat tree */ 301 #define CONFIG_OF_FLAT_TREE 1 302 #define CONFIG_OF_BOARD_SETUP 1 303 304 #define OF_CPU "PowerPC,8540@0" 305 #define OF_SOC "soc8540@e0000000" 306 #define OF_TBCLK (bd->bi_busfreq / 8) 307 #define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500" 308 309 #define CFG_64BIT_VSPRINTF 1 310 #define CFG_64BIT_STRTOUL 1 311 312 /* 313 * I2C 314 */ 315 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 316 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 317 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 318 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 319 #define CFG_I2C_SLAVE 0x7F 320 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 321 #define CFG_I2C_OFFSET 0x3000 322 323 /* RapidIO MMU */ 324 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 325 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 326 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 327 328 /* 329 * General PCI 330 * Memory space is mapped 1-1, but I/O space must start from 0. 331 */ 332 #define CFG_PCI1_MEM_BASE 0x80000000 333 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 334 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 335 #define CFG_PCI1_IO_BASE 0x00000000 336 #define CFG_PCI1_IO_PHYS 0xe2000000 337 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ 338 339 #if defined(CONFIG_PCI) 340 341 #define CONFIG_NET_MULTI 342 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 343 344 #undef CONFIG_EEPRO100 345 #undef CONFIG_TULIP 346 347 #if !defined(CONFIG_PCI_PNP) 348 #define PCI_ENET0_IOADDR 0xe0000000 349 #define PCI_ENET0_MEMADDR 0xe0000000 350 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 351 #endif 352 353 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 354 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 355 356 #endif /* CONFIG_PCI */ 357 358 359 #if defined(CONFIG_TSEC_ENET) 360 361 #ifndef CONFIG_NET_MULTI 362 #define CONFIG_NET_MULTI 1 363 #endif 364 365 #define CONFIG_MII 1 /* MII PHY management */ 366 #define CONFIG_TSEC1 1 367 #define CONFIG_TSEC1_NAME "TSEC0" 368 #define CONFIG_TSEC2 1 369 #define CONFIG_TSEC2_NAME "TSEC1" 370 #define TSEC1_PHY_ADDR 0 371 #define TSEC2_PHY_ADDR 1 372 #define TSEC1_PHYIDX 0 373 #define TSEC2_PHYIDX 0 374 #define TSEC1_FLAGS TSEC_GIGABIT 375 #define TSEC2_FLAGS TSEC_GIGABIT 376 377 378 #if CONFIG_HAS_FEC 379 #define CONFIG_MPC85XX_FEC 1 380 #define CONFIG_MPC85XX_FEC_NAME "FEC" 381 #define FEC_PHY_ADDR 3 382 #define FEC_PHYIDX 0 383 #define FEC_FLAGS 0 384 #endif 385 386 /* Options are: TSEC[0-1], FEC */ 387 #define CONFIG_ETHPRIME "TSEC0" 388 389 #endif /* CONFIG_TSEC_ENET */ 390 391 392 /* 393 * Environment 394 */ 395 #ifndef CFG_RAMBOOT 396 #define CFG_ENV_IS_IN_FLASH 1 397 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 398 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 399 #define CFG_ENV_SIZE 0x2000 400 #else 401 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 402 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 403 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 404 #define CFG_ENV_SIZE 0x2000 405 #endif 406 407 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 408 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 409 410 411 /* 412 * BOOTP options 413 */ 414 #define CONFIG_BOOTP_BOOTFILESIZE 415 #define CONFIG_BOOTP_BOOTPATH 416 #define CONFIG_BOOTP_GATEWAY 417 #define CONFIG_BOOTP_HOSTNAME 418 419 420 /* 421 * Command line configuration. 422 */ 423 #include <config_cmd_default.h> 424 425 #define CONFIG_CMD_PING 426 #define CONFIG_CMD_I2C 427 428 #if defined(CONFIG_PCI) 429 #define CONFIG_CMD_PCI 430 #endif 431 432 #if defined(CFG_RAMBOOT) 433 #undef CONFIG_CMD_ENV 434 #undef CONFIG_CMD_LOADS 435 #endif 436 437 438 #undef CONFIG_WATCHDOG /* watchdog disabled */ 439 440 /* 441 * Miscellaneous configurable options 442 */ 443 #define CFG_LONGHELP /* undef to save memory */ 444 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 445 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 446 447 #if defined(CONFIG_CMD_KGDB) 448 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 449 #else 450 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 451 #endif 452 453 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 454 #define CFG_MAXARGS 16 /* max number of command args */ 455 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 456 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 457 458 /* 459 * For booting Linux, the board info and command line data 460 * have to be in the first 8 MB of memory, since this is 461 * the maximum mapped by the Linux kernel during initialization. 462 */ 463 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 464 465 /* Cache Configuration */ 466 #define CFG_DCACHE_SIZE 32768 467 #define CFG_CACHELINE_SIZE 32 468 #if defined(CONFIG_CMD_KGDB) 469 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 470 #endif 471 472 /* 473 * Internal Definitions 474 * 475 * Boot Flags 476 */ 477 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 478 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 479 480 #if defined(CONFIG_CMD_KGDB) 481 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 482 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 483 #endif 484 485 486 /* 487 * Environment Configuration 488 */ 489 490 /* The mac addresses for all ethernet interface */ 491 #if defined(CONFIG_TSEC_ENET) 492 #define CONFIG_HAS_ETH0 493 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 494 #define CONFIG_HAS_ETH1 495 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 496 #define CONFIG_HAS_ETH2 497 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 498 #endif 499 500 #define CONFIG_IPADDR 192.168.1.253 501 502 #define CONFIG_HOSTNAME unknown 503 #define CONFIG_ROOTPATH /nfsroot 504 #define CONFIG_BOOTFILE your.uImage 505 506 #define CONFIG_SERVERIP 192.168.1.1 507 #define CONFIG_GATEWAYIP 192.168.1.1 508 #define CONFIG_NETMASK 255.255.255.0 509 510 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 511 512 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 513 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 514 515 #define CONFIG_BAUDRATE 115200 516 517 #define CONFIG_EXTRA_ENV_SETTINGS \ 518 "netdev=eth0\0" \ 519 "consoledev=ttyS0\0" \ 520 "ramdiskaddr=1000000\0" \ 521 "ramdiskfile=your.ramdisk.u-boot\0" \ 522 "fdtaddr=400000\0" \ 523 "fdtfile=your.fdt.dtb\0" 524 525 #define CONFIG_NFSBOOTCOMMAND \ 526 "setenv bootargs root=/dev/nfs rw " \ 527 "nfsroot=$serverip:$rootpath " \ 528 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 529 "console=$consoledev,$baudrate $othbootargs;" \ 530 "tftp $loadaddr $bootfile;" \ 531 "tftp $fdtaddr $fdtfile;" \ 532 "bootm $loadaddr - $fdtaddr" 533 534 #define CONFIG_RAMBOOTCOMMAND \ 535 "setenv bootargs root=/dev/ram rw " \ 536 "console=$consoledev,$baudrate $othbootargs;" \ 537 "tftp $ramdiskaddr $ramdiskfile;" \ 538 "tftp $loadaddr $bootfile;" \ 539 "tftp $fdtaddr $fdtfile;" \ 540 "bootm $loadaddr $ramdiskaddr $fdtaddr" 541 542 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 543 544 #endif /* __CONFIG_H */ 545