1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 #include "../board/freescale/common/ics307_clk.h" 17 18 #ifdef CONFIG_36BIT 19 #define CONFIG_PHYS_64BIT 1 20 #endif 21 22 #ifdef CONFIG_NAND 23 #define CONFIG_NAND_U_BOOT 1 24 #define CONFIG_RAMBOOT_NAND 1 25 #ifdef CONFIG_NAND_SPL 26 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 27 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 28 #else 29 #define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds 30 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 31 #endif /* CONFIG_NAND_SPL */ 32 #endif 33 34 #ifdef CONFIG_SDCARD 35 #define CONFIG_RAMBOOT_SDCARD 1 36 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 37 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 38 #endif 39 40 #ifdef CONFIG_SPIFLASH 41 #define CONFIG_RAMBOOT_SPIFLASH 1 42 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 43 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 44 #endif 45 46 #ifndef CONFIG_SYS_TEXT_BASE 47 #define CONFIG_SYS_TEXT_BASE 0xeff40000 48 #endif 49 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 52 #endif 53 54 #ifndef CONFIG_SYS_MONITOR_BASE 55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 56 #endif 57 58 /* High Level Configuration Options */ 59 #define CONFIG_BOOKE 1 /* BOOKE */ 60 #define CONFIG_E500 1 /* BOOKE e500 family */ 61 #define CONFIG_MPC8536 1 62 #define CONFIG_MPC8536DS 1 63 64 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 65 #define CONFIG_SPI_FLASH 1 /* Has SPI Flash */ 66 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 67 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 68 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 69 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 70 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 71 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 72 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 73 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 74 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 75 76 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 77 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 78 79 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 80 #define CONFIG_ENV_OVERWRITE 81 82 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 83 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 84 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 85 86 /* 87 * These can be toggled for performance analysis, otherwise use default. 88 */ 89 #define CONFIG_L2_CACHE /* toggle L2 cache */ 90 #define CONFIG_BTB /* toggle branch predition */ 91 92 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 93 94 #define CONFIG_ENABLE_36BIT_PHYS 1 95 96 #ifdef CONFIG_PHYS_64BIT 97 #define CONFIG_ADDR_MAP 1 98 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 99 #endif 100 101 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 102 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 103 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 104 105 /* 106 * Config the L2 Cache as L2 SRAM 107 */ 108 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 109 #ifdef CONFIG_PHYS_64BIT 110 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 111 #else 112 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 113 #endif 114 #define CONFIG_SYS_L2_SIZE (512 << 10) 115 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 116 117 #define CONFIG_SYS_CCSRBAR 0xffe00000 118 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 119 120 #if defined(CONFIG_NAND_SPL) 121 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 122 #endif 123 124 /* DDR Setup */ 125 #define CONFIG_VERY_BIG_RAM 126 #define CONFIG_SYS_FSL_DDR2 127 #undef CONFIG_FSL_DDR_INTERACTIVE 128 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 129 #define CONFIG_DDR_SPD 130 131 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 132 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 133 134 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 135 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 136 137 #define CONFIG_NUM_DDR_CONTROLLERS 1 138 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 139 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 140 141 /* I2C addresses of SPD EEPROMs */ 142 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 143 #define CONFIG_SYS_SPD_BUS_NUM 1 144 145 /* These are used when DDR doesn't use SPD. */ 146 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 147 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 148 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 149 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 150 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 151 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 152 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 153 #define CONFIG_SYS_DDR_MODE_1 0x00480432 154 #define CONFIG_SYS_DDR_MODE_2 0x00000000 155 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 156 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 157 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 158 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 159 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 160 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 161 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 162 163 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 164 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 165 #define CONFIG_SYS_DDR_SBE 0x00010000 166 167 /* Make sure required options are set */ 168 #ifndef CONFIG_SPD_EEPROM 169 #error ("CONFIG_SPD_EEPROM is required") 170 #endif 171 172 #undef CONFIG_CLOCKS_IN_MHZ 173 174 175 /* 176 * Memory map -- xxx -this is wrong, needs updating 177 * 178 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 179 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 180 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 181 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 182 * 183 * Localbus cacheable (TBD) 184 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 185 * 186 * Localbus non-cacheable 187 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 188 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 189 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 190 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 191 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 192 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 193 */ 194 195 /* 196 * Local Bus Definitions 197 */ 198 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 199 #ifdef CONFIG_PHYS_64BIT 200 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 201 #else 202 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 203 #endif 204 205 #define CONFIG_FLASH_BR_PRELIM \ 206 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 207 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 208 209 #define CONFIG_SYS_BR1_PRELIM \ 210 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 211 | BR_PS_16 | BR_V) 212 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 213 214 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 215 CONFIG_SYS_FLASH_BASE_PHYS } 216 #define CONFIG_SYS_FLASH_QUIET_TEST 217 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 218 219 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 220 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 221 #undef CONFIG_SYS_FLASH_CHECKSUM 222 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 223 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 224 225 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \ 226 defined(CONFIG_RAMBOOT_SPIFLASH) 227 #define CONFIG_SYS_RAMBOOT 228 #define CONFIG_SYS_EXTRA_ENV_RELOC 229 #else 230 #undef CONFIG_SYS_RAMBOOT 231 #endif 232 233 #define CONFIG_FLASH_CFI_DRIVER 234 #define CONFIG_SYS_FLASH_CFI 235 #define CONFIG_SYS_FLASH_EMPTY_INFO 236 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 237 238 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 239 240 #define CONFIG_HWCONFIG /* enable hwconfig */ 241 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 242 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 243 #ifdef CONFIG_PHYS_64BIT 244 #define PIXIS_BASE_PHYS 0xfffdf0000ull 245 #else 246 #define PIXIS_BASE_PHYS PIXIS_BASE 247 #endif 248 249 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 250 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 251 252 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 253 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 254 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 255 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 256 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 257 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 258 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 259 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 260 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 261 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 262 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 263 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 264 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 265 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 266 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 267 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 268 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 269 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 270 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 271 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 272 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 273 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 274 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 275 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 276 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 277 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 278 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 279 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 280 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 281 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 282 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 283 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 284 #define PIXIS_LED 0x25 /* LED Register */ 285 286 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 287 288 /* old pixis referenced names */ 289 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 290 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 291 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 292 293 #define CONFIG_SYS_INIT_RAM_LOCK 1 294 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 295 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 296 297 #define CONFIG_SYS_GBL_DATA_OFFSET \ 298 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 299 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 300 301 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 302 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 303 304 #ifndef CONFIG_NAND_SPL 305 #define CONFIG_SYS_NAND_BASE 0xffa00000 306 #ifdef CONFIG_PHYS_64BIT 307 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 308 #else 309 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 310 #endif 311 #else 312 #define CONFIG_SYS_NAND_BASE 0xfff00000 313 #ifdef CONFIG_PHYS_64BIT 314 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 315 #else 316 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 317 #endif 318 #endif 319 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 320 CONFIG_SYS_NAND_BASE + 0x40000, \ 321 CONFIG_SYS_NAND_BASE + 0x80000, \ 322 CONFIG_SYS_NAND_BASE + 0xC0000} 323 #define CONFIG_SYS_MAX_NAND_DEVICE 4 324 #define CONFIG_MTD_NAND_VERIFY_WRITE 325 #define CONFIG_CMD_NAND 1 326 #define CONFIG_NAND_FSL_ELBC 1 327 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 328 329 /* NAND boot: 4K NAND loader config */ 330 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 331 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 332 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 333 #define CONFIG_SYS_NAND_U_BOOT_START \ 334 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 335 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 336 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 337 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 338 339 /* NAND flash config */ 340 #define CONFIG_SYS_NAND_BR_PRELIM \ 341 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 342 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 343 | BR_PS_8 /* Port Size = 8 bit */ \ 344 | BR_MS_FCM /* MSEL = FCM */ \ 345 | BR_V) /* valid */ 346 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 347 | OR_FCM_PGS /* Large Page*/ \ 348 | OR_FCM_CSCT \ 349 | OR_FCM_CST \ 350 | OR_FCM_CHT \ 351 | OR_FCM_SCY_1 \ 352 | OR_FCM_TRLX \ 353 | OR_FCM_EHTR) 354 355 #ifdef CONFIG_RAMBOOT_NAND 356 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 357 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 358 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 359 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 360 #else 361 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 362 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 363 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 364 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 365 #endif 366 367 #define CONFIG_SYS_BR4_PRELIM \ 368 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 369 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 370 | BR_PS_8 /* Port Size = 8 bit */ \ 371 | BR_MS_FCM /* MSEL = FCM */ \ 372 | BR_V) /* valid */ 373 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 374 #define CONFIG_SYS_BR5_PRELIM \ 375 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 376 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 377 | BR_PS_8 /* Port Size = 8 bit */ \ 378 | BR_MS_FCM /* MSEL = FCM */ \ 379 | BR_V) /* valid */ 380 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 381 382 #define CONFIG_SYS_BR6_PRELIM \ 383 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 384 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 385 | BR_PS_8 /* Port Size = 8 bit */ \ 386 | BR_MS_FCM /* MSEL = FCM */ \ 387 | BR_V) /* valid */ 388 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 389 390 /* Serial Port - controlled on board with jumper J8 391 * open - index 2 392 * shorted - index 1 393 */ 394 #define CONFIG_CONS_INDEX 1 395 #define CONFIG_SYS_NS16550 396 #define CONFIG_SYS_NS16550_SERIAL 397 #define CONFIG_SYS_NS16550_REG_SIZE 1 398 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 399 #ifdef CONFIG_NAND_SPL 400 #define CONFIG_NS16550_MIN_FUNCTIONS 401 #endif 402 403 #define CONFIG_SYS_BAUDRATE_TABLE \ 404 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 405 406 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 407 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 408 409 /* Use the HUSH parser */ 410 #define CONFIG_SYS_HUSH_PARSER 411 412 /* 413 * Pass open firmware flat tree 414 */ 415 #define CONFIG_OF_LIBFDT 1 416 #define CONFIG_OF_BOARD_SETUP 1 417 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 418 419 /* 420 * I2C 421 */ 422 #define CONFIG_SYS_I2C 423 #define CONFIG_SYS_I2C_FSL 424 #define CONFIG_SYS_FSL_I2C_SPEED 400000 425 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 426 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 427 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 428 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 429 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 430 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 431 432 /* 433 * I2C2 EEPROM 434 */ 435 #define CONFIG_ID_EEPROM 436 #ifdef CONFIG_ID_EEPROM 437 #define CONFIG_SYS_I2C_EEPROM_NXID 438 #endif 439 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 440 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 441 #define CONFIG_SYS_EEPROM_BUS_NUM 1 442 443 /* 444 * eSPI - Enhanced SPI 445 */ 446 #define CONFIG_HARD_SPI 447 #define CONFIG_FSL_ESPI 448 449 #if defined(CONFIG_SPI_FLASH) 450 #define CONFIG_SPI_FLASH_SPANSION 451 #define CONFIG_CMD_SF 452 #define CONFIG_SF_DEFAULT_SPEED 10000000 453 #define CONFIG_SF_DEFAULT_MODE 0 454 #endif 455 456 /* 457 * General PCI 458 * Memory space is mapped 1-1, but I/O space must start from 0. 459 */ 460 461 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 464 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 465 #else 466 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 467 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 468 #endif 469 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 470 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 471 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 474 #else 475 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 476 #endif 477 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 478 479 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 480 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 481 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 482 #ifdef CONFIG_PHYS_64BIT 483 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 484 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 485 #else 486 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 487 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 488 #endif 489 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 490 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 491 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 492 #ifdef CONFIG_PHYS_64BIT 493 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 494 #else 495 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 496 #endif 497 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 498 499 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 500 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 501 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 502 #ifdef CONFIG_PHYS_64BIT 503 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 504 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 505 #else 506 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 507 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 508 #endif 509 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 510 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 511 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 512 #ifdef CONFIG_PHYS_64BIT 513 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 514 #else 515 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 516 #endif 517 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 518 519 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 520 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 521 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 522 #ifdef CONFIG_PHYS_64BIT 523 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 524 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 525 #else 526 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 527 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 528 #endif 529 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 530 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 531 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 532 #ifdef CONFIG_PHYS_64BIT 533 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 534 #else 535 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 536 #endif 537 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 538 539 #if defined(CONFIG_PCI) 540 541 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 542 543 /*PCIE video card used*/ 544 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 545 546 /*PCI video card used*/ 547 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 548 549 /* video */ 550 #define CONFIG_VIDEO 551 552 #if defined(CONFIG_VIDEO) 553 #define CONFIG_BIOSEMU 554 #define CONFIG_CFB_CONSOLE 555 #define CONFIG_VIDEO_SW_CURSOR 556 #define CONFIG_VGA_AS_SINGLE_DEVICE 557 #define CONFIG_ATI_RADEON_FB 558 #define CONFIG_VIDEO_LOGO 559 /*#define CONFIG_CONSOLE_CURSOR*/ 560 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 561 #endif 562 563 #undef CONFIG_EEPRO100 564 #undef CONFIG_TULIP 565 #undef CONFIG_RTL8139 566 567 #ifndef CONFIG_PCI_PNP 568 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 569 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 570 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 571 #endif 572 573 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 574 575 #endif /* CONFIG_PCI */ 576 577 /* SATA */ 578 #define CONFIG_LIBATA 579 #define CONFIG_FSL_SATA 580 581 #define CONFIG_SYS_SATA_MAX_DEVICE 2 582 #define CONFIG_SATA1 583 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 584 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 585 #define CONFIG_SATA2 586 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 587 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 588 589 #ifdef CONFIG_FSL_SATA 590 #define CONFIG_LBA48 591 #define CONFIG_CMD_SATA 592 #define CONFIG_DOS_PARTITION 593 #define CONFIG_CMD_EXT2 594 #endif 595 596 #if defined(CONFIG_TSEC_ENET) 597 598 #define CONFIG_MII 1 /* MII PHY management */ 599 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 600 #define CONFIG_TSEC1 1 601 #define CONFIG_TSEC1_NAME "eTSEC1" 602 #define CONFIG_TSEC3 1 603 #define CONFIG_TSEC3_NAME "eTSEC3" 604 605 #define CONFIG_FSL_SGMII_RISER 1 606 #define SGMII_RISER_PHY_OFFSET 0x1c 607 608 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 609 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 610 611 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 612 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 613 614 #define TSEC1_PHYIDX 0 615 #define TSEC3_PHYIDX 0 616 617 #define CONFIG_ETHPRIME "eTSEC1" 618 619 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 620 621 #endif /* CONFIG_TSEC_ENET */ 622 623 /* 624 * Environment 625 */ 626 627 #if defined(CONFIG_SYS_RAMBOOT) 628 #if defined(CONFIG_RAMBOOT_NAND) 629 #define CONFIG_ENV_IS_IN_NAND 1 630 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 631 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 632 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 633 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 634 #define CONFIG_ENV_IS_IN_SPI_FLASH 635 #define CONFIG_ENV_SPI_BUS 0 636 #define CONFIG_ENV_SPI_CS 0 637 #define CONFIG_ENV_SPI_MAX_HZ 10000000 638 #define CONFIG_ENV_SPI_MODE 0 639 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 640 #define CONFIG_ENV_OFFSET 0xF0000 641 #define CONFIG_ENV_SECT_SIZE 0x10000 642 #elif defined(CONFIG_RAMBOOT_SDCARD) 643 #define CONFIG_ENV_IS_IN_MMC 644 #define CONFIG_FSL_FIXED_MMC_LOCATION 645 #define CONFIG_ENV_SIZE 0x2000 646 #define CONFIG_SYS_MMC_ENV_DEV 0 647 #else 648 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 649 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 650 #define CONFIG_ENV_SIZE 0x2000 651 #endif 652 #else 653 #define CONFIG_ENV_IS_IN_FLASH 1 654 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 655 #define CONFIG_ENV_SIZE 0x2000 656 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 657 #endif 658 659 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 660 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 661 662 /* 663 * Command line configuration. 664 */ 665 #include <config_cmd_default.h> 666 667 #define CONFIG_CMD_IRQ 668 #define CONFIG_CMD_PING 669 #define CONFIG_CMD_I2C 670 #define CONFIG_CMD_MII 671 #define CONFIG_CMD_ELF 672 #define CONFIG_CMD_IRQ 673 #define CONFIG_CMD_SETEXPR 674 #define CONFIG_CMD_REGINFO 675 676 #if defined(CONFIG_PCI) 677 #define CONFIG_CMD_PCI 678 #define CONFIG_CMD_NET 679 #endif 680 681 #undef CONFIG_WATCHDOG /* watchdog disabled */ 682 683 #define CONFIG_MMC 1 684 685 #ifdef CONFIG_MMC 686 #define CONFIG_FSL_ESDHC 687 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 688 #define CONFIG_CMD_MMC 689 #define CONFIG_GENERIC_MMC 690 #endif 691 692 /* 693 * USB 694 */ 695 #define CONFIG_HAS_FSL_MPH_USB 696 #ifdef CONFIG_HAS_FSL_MPH_USB 697 #define CONFIG_USB_EHCI 698 699 #ifdef CONFIG_USB_EHCI 700 #define CONFIG_CMD_USB 701 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 702 #define CONFIG_USB_EHCI_FSL 703 #define CONFIG_USB_STORAGE 704 #endif 705 #endif 706 707 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 708 #define CONFIG_CMD_EXT2 709 #define CONFIG_CMD_FAT 710 #define CONFIG_DOS_PARTITION 711 #endif 712 713 /* 714 * Miscellaneous configurable options 715 */ 716 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 717 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 718 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 719 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 720 #if defined(CONFIG_CMD_KGDB) 721 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 722 #else 723 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 724 #endif 725 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 726 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 727 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 728 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 729 730 /* 731 * For booting Linux, the board info and command line data 732 * have to be in the first 64 MB of memory, since this is 733 * the maximum mapped by the Linux kernel during initialization. 734 */ 735 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 736 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 737 738 #if defined(CONFIG_CMD_KGDB) 739 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 740 #endif 741 742 /* 743 * Environment Configuration 744 */ 745 746 /* The mac addresses for all ethernet interface */ 747 #if defined(CONFIG_TSEC_ENET) 748 #define CONFIG_HAS_ETH0 749 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 750 #define CONFIG_HAS_ETH1 751 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 752 #define CONFIG_HAS_ETH2 753 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 754 #define CONFIG_HAS_ETH3 755 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 756 #endif 757 758 #define CONFIG_IPADDR 192.168.1.254 759 760 #define CONFIG_HOSTNAME unknown 761 #define CONFIG_ROOTPATH "/opt/nfsroot" 762 #define CONFIG_BOOTFILE "uImage" 763 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 764 765 #define CONFIG_SERVERIP 192.168.1.1 766 #define CONFIG_GATEWAYIP 192.168.1.1 767 #define CONFIG_NETMASK 255.255.255.0 768 769 /* default location for tftp and bootm */ 770 #define CONFIG_LOADADDR 1000000 771 772 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 773 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 774 775 #define CONFIG_BAUDRATE 115200 776 777 #define CONFIG_EXTRA_ENV_SETTINGS \ 778 "netdev=eth0\0" \ 779 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 780 "tftpflash=tftpboot $loadaddr $uboot; " \ 781 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 782 " +$filesize; " \ 783 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 784 " +$filesize; " \ 785 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 786 " $filesize; " \ 787 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 788 " +$filesize; " \ 789 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 790 " $filesize\0" \ 791 "consoledev=ttyS0\0" \ 792 "ramdiskaddr=2000000\0" \ 793 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 794 "fdtaddr=c00000\0" \ 795 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 796 "bdev=sda3\0" \ 797 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 798 799 #define CONFIG_HDBOOT \ 800 "setenv bootargs root=/dev/$bdev rw " \ 801 "console=$consoledev,$baudrate $othbootargs;" \ 802 "tftp $loadaddr $bootfile;" \ 803 "tftp $fdtaddr $fdtfile;" \ 804 "bootm $loadaddr - $fdtaddr" 805 806 #define CONFIG_NFSBOOTCOMMAND \ 807 "setenv bootargs root=/dev/nfs rw " \ 808 "nfsroot=$serverip:$rootpath " \ 809 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 810 "console=$consoledev,$baudrate $othbootargs;" \ 811 "tftp $loadaddr $bootfile;" \ 812 "tftp $fdtaddr $fdtfile;" \ 813 "bootm $loadaddr - $fdtaddr" 814 815 #define CONFIG_RAMBOOTCOMMAND \ 816 "setenv bootargs root=/dev/ram rw " \ 817 "console=$consoledev,$baudrate $othbootargs;" \ 818 "tftp $ramdiskaddr $ramdiskfile;" \ 819 "tftp $loadaddr $bootfile;" \ 820 "tftp $fdtaddr $fdtfile;" \ 821 "bootm $loadaddr $ramdiskaddr $fdtaddr" 822 823 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 824 825 #endif /* __CONFIG_H */ 826