1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #include "../board/freescale/common/ics307_clk.h" 16 17 #ifdef CONFIG_SDCARD 18 #define CONFIG_RAMBOOT_SDCARD 1 19 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 20 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 21 #endif 22 23 #ifdef CONFIG_SPIFLASH 24 #define CONFIG_RAMBOOT_SPIFLASH 1 25 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 27 #endif 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff40000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #ifndef CONFIG_SYS_MONITOR_BASE 38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 39 #endif 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE 1 /* BOOKE */ 43 #define CONFIG_E500 1 /* BOOKE e500 family */ 44 #define CONFIG_MPC8536 1 45 #define CONFIG_MPC8536DS 1 46 47 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 48 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 49 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 50 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 51 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 52 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 53 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 54 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 55 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 56 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 57 58 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 59 60 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 61 #define CONFIG_ENV_OVERWRITE 62 63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 64 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 65 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 66 67 /* 68 * These can be toggled for performance analysis, otherwise use default. 69 */ 70 #define CONFIG_L2_CACHE /* toggle L2 cache */ 71 #define CONFIG_BTB /* toggle branch predition */ 72 73 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 74 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #ifdef CONFIG_PHYS_64BIT 78 #define CONFIG_ADDR_MAP 1 79 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 80 #endif 81 82 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 83 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 84 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 85 86 /* 87 * Config the L2 Cache as L2 SRAM 88 */ 89 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 90 #ifdef CONFIG_PHYS_64BIT 91 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 92 #else 93 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 94 #endif 95 #define CONFIG_SYS_L2_SIZE (512 << 10) 96 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 97 98 #define CONFIG_SYS_CCSRBAR 0xffe00000 99 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 100 101 #if defined(CONFIG_NAND_SPL) 102 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 103 #endif 104 105 /* DDR Setup */ 106 #define CONFIG_VERY_BIG_RAM 107 #define CONFIG_SYS_FSL_DDR2 108 #undef CONFIG_FSL_DDR_INTERACTIVE 109 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 110 #define CONFIG_DDR_SPD 111 112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 113 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 114 115 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 117 118 #define CONFIG_NUM_DDR_CONTROLLERS 1 119 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 120 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 121 122 /* I2C addresses of SPD EEPROMs */ 123 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 124 #define CONFIG_SYS_SPD_BUS_NUM 1 125 126 /* These are used when DDR doesn't use SPD. */ 127 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 128 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 129 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 130 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 131 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 132 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 133 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 134 #define CONFIG_SYS_DDR_MODE_1 0x00480432 135 #define CONFIG_SYS_DDR_MODE_2 0x00000000 136 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 137 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 138 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 139 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 140 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 141 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 142 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 143 144 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 145 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 146 #define CONFIG_SYS_DDR_SBE 0x00010000 147 148 /* Make sure required options are set */ 149 #ifndef CONFIG_SPD_EEPROM 150 #error ("CONFIG_SPD_EEPROM is required") 151 #endif 152 153 #undef CONFIG_CLOCKS_IN_MHZ 154 155 /* 156 * Memory map -- xxx -this is wrong, needs updating 157 * 158 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 159 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 160 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 161 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 162 * 163 * Localbus cacheable (TBD) 164 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 165 * 166 * Localbus non-cacheable 167 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 168 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 169 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 170 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 171 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 172 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 173 */ 174 175 /* 176 * Local Bus Definitions 177 */ 178 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 179 #ifdef CONFIG_PHYS_64BIT 180 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 181 #else 182 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 183 #endif 184 185 #define CONFIG_FLASH_BR_PRELIM \ 186 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 187 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 188 189 #define CONFIG_SYS_BR1_PRELIM \ 190 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 191 | BR_PS_16 | BR_V) 192 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 193 194 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 195 CONFIG_SYS_FLASH_BASE_PHYS } 196 #define CONFIG_SYS_FLASH_QUIET_TEST 197 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 198 199 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 200 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 201 #undef CONFIG_SYS_FLASH_CHECKSUM 202 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 203 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 204 205 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 206 #define CONFIG_SYS_RAMBOOT 207 #define CONFIG_SYS_EXTRA_ENV_RELOC 208 #else 209 #undef CONFIG_SYS_RAMBOOT 210 #endif 211 212 #define CONFIG_FLASH_CFI_DRIVER 213 #define CONFIG_SYS_FLASH_CFI 214 #define CONFIG_SYS_FLASH_EMPTY_INFO 215 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 216 217 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 218 219 #define CONFIG_HWCONFIG /* enable hwconfig */ 220 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 221 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 222 #ifdef CONFIG_PHYS_64BIT 223 #define PIXIS_BASE_PHYS 0xfffdf0000ull 224 #else 225 #define PIXIS_BASE_PHYS PIXIS_BASE 226 #endif 227 228 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 229 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 230 231 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 232 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 233 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 234 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 235 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 236 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 237 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 238 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 239 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 240 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 241 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 242 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 243 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 244 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 245 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 246 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 247 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 248 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 249 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 250 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 251 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 252 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 253 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 254 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 255 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 256 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 257 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 258 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 259 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 260 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 261 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 262 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 263 #define PIXIS_LED 0x25 /* LED Register */ 264 265 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 266 267 /* old pixis referenced names */ 268 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 269 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 270 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 271 272 #define CONFIG_SYS_INIT_RAM_LOCK 1 273 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 274 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 275 276 #define CONFIG_SYS_GBL_DATA_OFFSET \ 277 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 278 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 279 280 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 281 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 282 283 #ifndef CONFIG_NAND_SPL 284 #define CONFIG_SYS_NAND_BASE 0xffa00000 285 #ifdef CONFIG_PHYS_64BIT 286 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 287 #else 288 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 289 #endif 290 #else 291 #define CONFIG_SYS_NAND_BASE 0xfff00000 292 #ifdef CONFIG_PHYS_64BIT 293 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 294 #else 295 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 296 #endif 297 #endif 298 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 299 CONFIG_SYS_NAND_BASE + 0x40000, \ 300 CONFIG_SYS_NAND_BASE + 0x80000, \ 301 CONFIG_SYS_NAND_BASE + 0xC0000} 302 #define CONFIG_SYS_MAX_NAND_DEVICE 4 303 #define CONFIG_CMD_NAND 1 304 #define CONFIG_NAND_FSL_ELBC 1 305 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 306 307 /* NAND boot: 4K NAND loader config */ 308 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 309 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 310 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 311 #define CONFIG_SYS_NAND_U_BOOT_START \ 312 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 313 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 314 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 315 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 316 317 /* NAND flash config */ 318 #define CONFIG_SYS_NAND_BR_PRELIM \ 319 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 320 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 321 | BR_PS_8 /* Port Size = 8 bit */ \ 322 | BR_MS_FCM /* MSEL = FCM */ \ 323 | BR_V) /* valid */ 324 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 325 | OR_FCM_PGS /* Large Page*/ \ 326 | OR_FCM_CSCT \ 327 | OR_FCM_CST \ 328 | OR_FCM_CHT \ 329 | OR_FCM_SCY_1 \ 330 | OR_FCM_TRLX \ 331 | OR_FCM_EHTR) 332 333 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 334 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 335 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 336 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 337 338 #define CONFIG_SYS_BR4_PRELIM \ 339 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 340 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 341 | BR_PS_8 /* Port Size = 8 bit */ \ 342 | BR_MS_FCM /* MSEL = FCM */ \ 343 | BR_V) /* valid */ 344 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 345 #define CONFIG_SYS_BR5_PRELIM \ 346 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 347 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 348 | BR_PS_8 /* Port Size = 8 bit */ \ 349 | BR_MS_FCM /* MSEL = FCM */ \ 350 | BR_V) /* valid */ 351 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 352 353 #define CONFIG_SYS_BR6_PRELIM \ 354 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 355 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 356 | BR_PS_8 /* Port Size = 8 bit */ \ 357 | BR_MS_FCM /* MSEL = FCM */ \ 358 | BR_V) /* valid */ 359 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 360 361 /* Serial Port - controlled on board with jumper J8 362 * open - index 2 363 * shorted - index 1 364 */ 365 #define CONFIG_CONS_INDEX 1 366 #define CONFIG_SYS_NS16550_SERIAL 367 #define CONFIG_SYS_NS16550_REG_SIZE 1 368 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 369 #ifdef CONFIG_NAND_SPL 370 #define CONFIG_NS16550_MIN_FUNCTIONS 371 #endif 372 373 #define CONFIG_SYS_BAUDRATE_TABLE \ 374 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 375 376 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 377 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 378 379 /* 380 * I2C 381 */ 382 #define CONFIG_SYS_I2C 383 #define CONFIG_SYS_I2C_FSL 384 #define CONFIG_SYS_FSL_I2C_SPEED 400000 385 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 386 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 387 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 388 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 389 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 390 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 391 392 /* 393 * I2C2 EEPROM 394 */ 395 #define CONFIG_ID_EEPROM 396 #ifdef CONFIG_ID_EEPROM 397 #define CONFIG_SYS_I2C_EEPROM_NXID 398 #endif 399 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 400 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 401 #define CONFIG_SYS_EEPROM_BUS_NUM 1 402 403 /* 404 * eSPI - Enhanced SPI 405 */ 406 #define CONFIG_HARD_SPI 407 408 #if defined(CONFIG_SPI_FLASH) 409 #define CONFIG_SF_DEFAULT_SPEED 10000000 410 #define CONFIG_SF_DEFAULT_MODE 0 411 #endif 412 413 /* 414 * General PCI 415 * Memory space is mapped 1-1, but I/O space must start from 0. 416 */ 417 418 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 419 #ifdef CONFIG_PHYS_64BIT 420 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 421 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 422 #else 423 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 424 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 425 #endif 426 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 427 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 428 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 429 #ifdef CONFIG_PHYS_64BIT 430 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 431 #else 432 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 433 #endif 434 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 435 436 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 437 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 438 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 439 #ifdef CONFIG_PHYS_64BIT 440 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 441 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 442 #else 443 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 444 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 445 #endif 446 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 447 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 448 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 449 #ifdef CONFIG_PHYS_64BIT 450 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 451 #else 452 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 453 #endif 454 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 455 456 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 457 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 458 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 461 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 462 #else 463 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 464 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 465 #endif 466 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 467 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 468 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 469 #ifdef CONFIG_PHYS_64BIT 470 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 471 #else 472 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 473 #endif 474 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 475 476 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 477 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 478 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 479 #ifdef CONFIG_PHYS_64BIT 480 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 481 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 482 #else 483 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 484 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 485 #endif 486 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 487 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 488 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 491 #else 492 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 493 #endif 494 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 495 496 #if defined(CONFIG_PCI) 497 498 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 499 500 /*PCIE video card used*/ 501 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 502 503 /*PCI video card used*/ 504 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 505 506 /* video */ 507 #define CONFIG_VIDEO 508 509 #if defined(CONFIG_VIDEO) 510 #define CONFIG_BIOSEMU 511 #define CONFIG_CFB_CONSOLE 512 #define CONFIG_VIDEO_SW_CURSOR 513 #define CONFIG_VGA_AS_SINGLE_DEVICE 514 #define CONFIG_ATI_RADEON_FB 515 #define CONFIG_VIDEO_LOGO 516 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 517 #endif 518 519 #undef CONFIG_EEPRO100 520 #undef CONFIG_TULIP 521 522 #ifndef CONFIG_PCI_PNP 523 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 524 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 525 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 526 #endif 527 528 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 529 530 #endif /* CONFIG_PCI */ 531 532 /* SATA */ 533 #define CONFIG_LIBATA 534 #define CONFIG_FSL_SATA 535 536 #define CONFIG_SYS_SATA_MAX_DEVICE 2 537 #define CONFIG_SATA1 538 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 539 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 540 #define CONFIG_SATA2 541 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 542 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 543 544 #ifdef CONFIG_FSL_SATA 545 #define CONFIG_LBA48 546 #define CONFIG_CMD_SATA 547 #define CONFIG_DOS_PARTITION 548 #endif 549 550 #if defined(CONFIG_TSEC_ENET) 551 552 #define CONFIG_MII 1 /* MII PHY management */ 553 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 554 #define CONFIG_TSEC1 1 555 #define CONFIG_TSEC1_NAME "eTSEC1" 556 #define CONFIG_TSEC3 1 557 #define CONFIG_TSEC3_NAME "eTSEC3" 558 559 #define CONFIG_FSL_SGMII_RISER 1 560 #define SGMII_RISER_PHY_OFFSET 0x1c 561 562 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 563 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 564 565 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 566 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 567 568 #define TSEC1_PHYIDX 0 569 #define TSEC3_PHYIDX 0 570 571 #define CONFIG_ETHPRIME "eTSEC1" 572 573 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 574 575 #endif /* CONFIG_TSEC_ENET */ 576 577 /* 578 * Environment 579 */ 580 581 #if defined(CONFIG_SYS_RAMBOOT) 582 #if defined(CONFIG_RAMBOOT_SPIFLASH) 583 #define CONFIG_ENV_IS_IN_SPI_FLASH 584 #define CONFIG_ENV_SPI_BUS 0 585 #define CONFIG_ENV_SPI_CS 0 586 #define CONFIG_ENV_SPI_MAX_HZ 10000000 587 #define CONFIG_ENV_SPI_MODE 0 588 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 589 #define CONFIG_ENV_OFFSET 0xF0000 590 #define CONFIG_ENV_SECT_SIZE 0x10000 591 #elif defined(CONFIG_RAMBOOT_SDCARD) 592 #define CONFIG_ENV_IS_IN_MMC 593 #define CONFIG_FSL_FIXED_MMC_LOCATION 594 #define CONFIG_ENV_SIZE 0x2000 595 #define CONFIG_SYS_MMC_ENV_DEV 0 596 #else 597 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 598 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 599 #define CONFIG_ENV_SIZE 0x2000 600 #endif 601 #else 602 #define CONFIG_ENV_IS_IN_FLASH 1 603 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 604 #define CONFIG_ENV_SIZE 0x2000 605 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 606 #endif 607 608 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 609 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 610 611 /* 612 * Command line configuration. 613 */ 614 #define CONFIG_CMD_IRQ 615 #define CONFIG_CMD_IRQ 616 #define CONFIG_CMD_REGINFO 617 618 #if defined(CONFIG_PCI) 619 #define CONFIG_CMD_PCI 620 #endif 621 622 #undef CONFIG_WATCHDOG /* watchdog disabled */ 623 624 #define CONFIG_MMC 1 625 626 #ifdef CONFIG_MMC 627 #define CONFIG_FSL_ESDHC 628 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 629 #define CONFIG_GENERIC_MMC 630 #endif 631 632 /* 633 * USB 634 */ 635 #define CONFIG_HAS_FSL_MPH_USB 636 #ifdef CONFIG_HAS_FSL_MPH_USB 637 #define CONFIG_USB_EHCI 638 639 #ifdef CONFIG_USB_EHCI 640 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 641 #define CONFIG_USB_EHCI_FSL 642 #define CONFIG_USB_STORAGE 643 #endif 644 #endif 645 646 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 647 #define CONFIG_DOS_PARTITION 648 #endif 649 650 /* 651 * Miscellaneous configurable options 652 */ 653 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 654 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 655 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 656 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 657 #if defined(CONFIG_CMD_KGDB) 658 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 659 #else 660 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 661 #endif 662 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 663 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 664 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 665 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 666 667 /* 668 * For booting Linux, the board info and command line data 669 * have to be in the first 64 MB of memory, since this is 670 * the maximum mapped by the Linux kernel during initialization. 671 */ 672 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 673 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 674 675 #if defined(CONFIG_CMD_KGDB) 676 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 677 #endif 678 679 /* 680 * Environment Configuration 681 */ 682 683 /* The mac addresses for all ethernet interface */ 684 #if defined(CONFIG_TSEC_ENET) 685 #define CONFIG_HAS_ETH0 686 #define CONFIG_HAS_ETH1 687 #define CONFIG_HAS_ETH2 688 #define CONFIG_HAS_ETH3 689 #endif 690 691 #define CONFIG_IPADDR 192.168.1.254 692 693 #define CONFIG_HOSTNAME unknown 694 #define CONFIG_ROOTPATH "/opt/nfsroot" 695 #define CONFIG_BOOTFILE "uImage" 696 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 697 698 #define CONFIG_SERVERIP 192.168.1.1 699 #define CONFIG_GATEWAYIP 192.168.1.1 700 #define CONFIG_NETMASK 255.255.255.0 701 702 /* default location for tftp and bootm */ 703 #define CONFIG_LOADADDR 1000000 704 705 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 706 707 #define CONFIG_BAUDRATE 115200 708 709 #define CONFIG_EXTRA_ENV_SETTINGS \ 710 "netdev=eth0\0" \ 711 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 712 "tftpflash=tftpboot $loadaddr $uboot; " \ 713 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 714 " +$filesize; " \ 715 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 716 " +$filesize; " \ 717 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 718 " $filesize; " \ 719 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 720 " +$filesize; " \ 721 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 722 " $filesize\0" \ 723 "consoledev=ttyS0\0" \ 724 "ramdiskaddr=2000000\0" \ 725 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 726 "fdtaddr=1e00000\0" \ 727 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 728 "bdev=sda3\0" \ 729 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 730 731 #define CONFIG_HDBOOT \ 732 "setenv bootargs root=/dev/$bdev rw " \ 733 "console=$consoledev,$baudrate $othbootargs;" \ 734 "tftp $loadaddr $bootfile;" \ 735 "tftp $fdtaddr $fdtfile;" \ 736 "bootm $loadaddr - $fdtaddr" 737 738 #define CONFIG_NFSBOOTCOMMAND \ 739 "setenv bootargs root=/dev/nfs rw " \ 740 "nfsroot=$serverip:$rootpath " \ 741 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 742 "console=$consoledev,$baudrate $othbootargs;" \ 743 "tftp $loadaddr $bootfile;" \ 744 "tftp $fdtaddr $fdtfile;" \ 745 "bootm $loadaddr - $fdtaddr" 746 747 #define CONFIG_RAMBOOTCOMMAND \ 748 "setenv bootargs root=/dev/ram rw " \ 749 "console=$consoledev,$baudrate $othbootargs;" \ 750 "tftp $ramdiskaddr $ramdiskfile;" \ 751 "tftp $loadaddr $bootfile;" \ 752 "tftp $fdtaddr $fdtfile;" \ 753 "bootm $loadaddr $ramdiskaddr $fdtaddr" 754 755 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 756 757 #endif /* __CONFIG_H */ 758