1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8536 1 35 #define CONFIG_MPC8536DS 1 36 37 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 38 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 39 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 40 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 41 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 42 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 46 47 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 48 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 52 /* 53 * When initializing flash, if we cannot find the manufacturer ID, 54 * assume this is the AMD flash associated with the CDS board. 55 * This allows booting from a promjet. 56 */ 57 #define CONFIG_ASSUME_AMD_FLASH 58 59 #ifndef __ASSEMBLY__ 60 extern unsigned long get_board_sys_clk(unsigned long dummy); 61 extern unsigned long get_board_ddr_clk(unsigned long dummy); 62 #endif 63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 64 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) 65 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 66 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 67 from ICS307 instead of switches */ 68 69 /* 70 * These can be toggled for performance analysis, otherwise use default. 71 */ 72 #define CONFIG_L2_CACHE /* toggle L2 cache */ 73 #define CONFIG_BTB /* toggle branch predition */ 74 75 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 76 77 #define CONFIG_ENABLE_36BIT_PHYS 1 78 79 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 80 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 81 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 82 83 /* 84 * Base addresses -- Note these are effective addresses where the 85 * actual resources get mapped (not physical addresses) 86 */ 87 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 88 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 89 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 90 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 91 92 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 93 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 94 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 95 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) 96 97 /* DDR Setup */ 98 #define CONFIG_FSL_DDR2 99 #undef CONFIG_FSL_DDR_INTERACTIVE 100 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 101 #define CONFIG_DDR_SPD 102 #undef CONFIG_DDR_DLL 103 104 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 105 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 106 107 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 109 110 #define CONFIG_NUM_DDR_CONTROLLERS 1 111 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 112 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 113 114 /* I2C addresses of SPD EEPROMs */ 115 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 116 #define CONFIG_SYS_SPD_BUS_NUM 1 117 118 /* These are used when DDR doesn't use SPD. */ 119 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 120 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 121 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 122 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 123 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 124 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 125 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 126 #define CONFIG_SYS_DDR_MODE_1 0x00480432 127 #define CONFIG_SYS_DDR_MODE_2 0x00000000 128 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 129 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 130 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 131 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 132 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 133 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 134 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 135 136 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 137 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 138 #define CONFIG_SYS_DDR_SBE 0x00010000 139 140 /* Make sure required options are set */ 141 #ifndef CONFIG_SPD_EEPROM 142 #error ("CONFIG_SPD_EEPROM is required") 143 #endif 144 145 #undef CONFIG_CLOCKS_IN_MHZ 146 147 148 /* 149 * Memory map -- xxx -this is wrong, needs updating 150 * 151 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 152 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 153 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 154 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 155 * 156 * Localbus cacheable (TBD) 157 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 158 * 159 * Localbus non-cacheable 160 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 161 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 162 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 163 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 164 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 165 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 166 */ 167 168 /* 169 * Local Bus Definitions 170 */ 171 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 172 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 173 174 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 175 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 176 177 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 178 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 179 180 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} 181 #define CONFIG_SYS_FLASH_QUIET_TEST 182 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 183 184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 185 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 186 #undef CONFIG_SYS_FLASH_CHECKSUM 187 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 188 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 189 190 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 191 192 #define CONFIG_FLASH_CFI_DRIVER 193 #define CONFIG_SYS_FLASH_CFI 194 #define CONFIG_SYS_FLASH_EMPTY_INFO 195 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 196 197 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 198 199 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 200 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 201 #define PIXIS_BASE_PHYS PIXIS_BASE 202 203 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 204 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 205 206 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 207 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 208 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 209 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 210 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 211 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 212 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 213 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 214 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 215 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 216 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 217 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 218 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 219 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 220 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 221 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 222 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 223 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 224 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 225 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 226 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 227 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 228 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 229 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 230 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 231 #define PIXIS_LED 0x25 /* LED Register */ 232 233 /* old pixis referenced names */ 234 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 235 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 236 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 237 238 #define CONFIG_SYS_INIT_RAM_LOCK 1 239 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 240 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 241 242 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 243 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 244 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 245 246 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 247 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 248 249 #define CONFIG_SYS_NAND_BASE 0xffa00000 250 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 251 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 252 CONFIG_SYS_NAND_BASE + 0x40000, \ 253 CONFIG_SYS_NAND_BASE + 0x80000, \ 254 CONFIG_SYS_NAND_BASE + 0xC0000} 255 #define CONFIG_SYS_MAX_NAND_DEVICE 4 256 #define CONFIG_MTD_NAND_VERIFY_WRITE 257 #define CONFIG_CMD_NAND 1 258 #define CONFIG_NAND_FSL_ELBC 1 259 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 260 261 /* NAND flash config */ 262 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 263 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 264 | BR_PS_8 /* Port Size = 8 bit */ \ 265 | BR_MS_FCM /* MSEL = FCM */ \ 266 | BR_V) /* valid */ 267 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 268 | OR_FCM_PGS /* Large Page*/ \ 269 | OR_FCM_CSCT \ 270 | OR_FCM_CST \ 271 | OR_FCM_CHT \ 272 | OR_FCM_SCY_1 \ 273 | OR_FCM_TRLX \ 274 | OR_FCM_EHTR) 275 276 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 277 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 278 279 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 280 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 281 | BR_PS_8 /* Port Size = 8 bit */ \ 282 | BR_MS_FCM /* MSEL = FCM */ \ 283 | BR_V) /* valid */ 284 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 285 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 286 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 287 | BR_PS_8 /* Port Size = 8 bit */ \ 288 | BR_MS_FCM /* MSEL = FCM */ \ 289 | BR_V) /* valid */ 290 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 291 292 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 293 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 294 | BR_PS_8 /* Port Size = 8 bit */ \ 295 | BR_MS_FCM /* MSEL = FCM */ \ 296 | BR_V) /* valid */ 297 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 298 299 /* Serial Port - controlled on board with jumper J8 300 * open - index 2 301 * shorted - index 1 302 */ 303 #define CONFIG_CONS_INDEX 1 304 #undef CONFIG_SERIAL_SOFTWARE_FIFO 305 #define CONFIG_SYS_NS16550 306 #define CONFIG_SYS_NS16550_SERIAL 307 #define CONFIG_SYS_NS16550_REG_SIZE 1 308 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 309 310 #define CONFIG_SYS_BAUDRATE_TABLE \ 311 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 312 313 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 314 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 315 316 /* Use the HUSH parser */ 317 #define CONFIG_SYS_HUSH_PARSER 318 #ifdef CONFIG_SYS_HUSH_PARSER 319 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 320 #endif 321 322 /* 323 * Pass open firmware flat tree 324 */ 325 #define CONFIG_OF_LIBFDT 1 326 #define CONFIG_OF_BOARD_SETUP 1 327 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 328 329 #define CONFIG_SYS_64BIT_STRTOUL 1 330 #define CONFIG_SYS_64BIT_VSPRINTF 1 331 332 333 /* 334 * I2C 335 */ 336 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 337 #define CONFIG_HARD_I2C /* I2C with hardware support */ 338 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 339 #define CONFIG_I2C_MULTI_BUS 340 #define CONFIG_I2C_CMD_TREE 341 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 342 #define CONFIG_SYS_I2C_SLAVE 0x7F 343 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 344 #define CONFIG_SYS_I2C_OFFSET 0x3000 345 #define CONFIG_SYS_I2C2_OFFSET 0x3100 346 347 /* 348 * I2C2 EEPROM 349 */ 350 #define CONFIG_ID_EEPROM 351 #ifdef CONFIG_ID_EEPROM 352 #define CONFIG_SYS_I2C_EEPROM_NXID 353 #endif 354 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 355 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 356 #define CONFIG_SYS_EEPROM_BUS_NUM 1 357 358 /* 359 * General PCI 360 * Memory space is mapped 1-1, but I/O space must start from 0. 361 */ 362 363 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 364 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 365 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 366 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 367 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 368 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 369 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 370 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 371 372 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 373 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 374 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 375 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 376 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 377 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 378 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 379 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 380 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 381 382 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 383 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 384 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 385 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 386 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 387 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 388 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 389 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 390 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 391 392 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 393 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 394 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 395 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 396 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 397 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 398 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 399 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 400 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 401 402 #if defined(CONFIG_PCI) 403 404 #define CONFIG_NET_MULTI 405 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 406 407 /*PCIE video card used*/ 408 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 409 410 /*PCI video card used*/ 411 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 412 413 /* video */ 414 #define CONFIG_VIDEO 415 416 #if defined(CONFIG_VIDEO) 417 #define CONFIG_BIOSEMU 418 #define CONFIG_CFB_CONSOLE 419 #define CONFIG_VIDEO_SW_CURSOR 420 #define CONFIG_VGA_AS_SINGLE_DEVICE 421 #define CONFIG_ATI_RADEON_FB 422 #define CONFIG_VIDEO_LOGO 423 /*#define CONFIG_CONSOLE_CURSOR*/ 424 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 425 #endif 426 427 #undef CONFIG_EEPRO100 428 #undef CONFIG_TULIP 429 #undef CONFIG_RTL8139 430 431 #ifdef CONFIG_RTL8139 432 /* This macro is used by RTL8139 but not defined in PPC architecture */ 433 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 434 #define _IO_BASE 0x00000000 435 #endif 436 437 #ifndef CONFIG_PCI_PNP 438 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 439 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 440 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 441 #endif 442 443 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 444 445 #endif /* CONFIG_PCI */ 446 447 /* SATA */ 448 #define CONFIG_LIBATA 449 #define CONFIG_FSL_SATA 450 451 #define CONFIG_SYS_SATA_MAX_DEVICE 2 452 #define CONFIG_SATA1 453 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 454 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 455 #define CONFIG_SATA2 456 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 457 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 458 459 #ifdef CONFIG_FSL_SATA 460 #define CONFIG_LBA48 461 #define CONFIG_CMD_SATA 462 #define CONFIG_DOS_PARTITION 463 #define CONFIG_CMD_EXT2 464 #endif 465 466 #if defined(CONFIG_TSEC_ENET) 467 468 #ifndef CONFIG_NET_MULTI 469 #define CONFIG_NET_MULTI 1 470 #endif 471 472 #define CONFIG_MII 1 /* MII PHY management */ 473 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 474 #define CONFIG_TSEC1 1 475 #define CONFIG_TSEC1_NAME "eTSEC1" 476 #define CONFIG_TSEC3 1 477 #define CONFIG_TSEC3_NAME "eTSEC3" 478 479 #define CONFIG_FSL_SGMII_RISER 1 480 #define SGMII_RISER_PHY_OFFSET 0x1c 481 482 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 483 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 484 485 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 486 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 487 488 #define TSEC1_PHYIDX 0 489 #define TSEC3_PHYIDX 0 490 491 #define CONFIG_ETHPRIME "eTSEC1" 492 493 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 494 495 #endif /* CONFIG_TSEC_ENET */ 496 497 /* 498 * Environment 499 */ 500 #define CONFIG_ENV_IS_IN_FLASH 1 501 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 502 #define CONFIG_ENV_ADDR 0xfff80000 503 #else 504 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 505 #endif 506 #define CONFIG_ENV_SIZE 0x2000 507 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 508 509 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 510 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 511 512 /* 513 * Command line configuration. 514 */ 515 #include <config_cmd_default.h> 516 517 #define CONFIG_CMD_IRQ 518 #define CONFIG_CMD_PING 519 #define CONFIG_CMD_I2C 520 #define CONFIG_CMD_MII 521 #define CONFIG_CMD_ELF 522 #define CONFIG_CMD_IRQ 523 #define CONFIG_CMD_SETEXPR 524 525 #if defined(CONFIG_PCI) 526 #define CONFIG_CMD_PCI 527 #define CONFIG_CMD_BEDBUG 528 #define CONFIG_CMD_NET 529 #endif 530 531 #undef CONFIG_WATCHDOG /* watchdog disabled */ 532 533 #define CONFIG_MMC 1 534 535 #ifdef CONFIG_MMC 536 #define CONFIG_FSL_ESDHC 537 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 538 #define CONFIG_CMD_MMC 539 #define CONFIG_GENERIC_MMC 540 #define CONFIG_CMD_EXT2 541 #define CONFIG_CMD_FAT 542 #define CONFIG_DOS_PARTITION 543 #endif 544 545 /* 546 * Miscellaneous configurable options 547 */ 548 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 549 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 550 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 551 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 552 #if defined(CONFIG_CMD_KGDB) 553 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 554 #else 555 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 556 #endif 557 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 558 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 559 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 560 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 561 562 /* 563 * For booting Linux, the board info and command line data 564 * have to be in the first 8 MB of memory, since this is 565 * the maximum mapped by the Linux kernel during initialization. 566 */ 567 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 568 569 /* 570 * Internal Definitions 571 * 572 * Boot Flags 573 */ 574 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 575 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 576 577 #if defined(CONFIG_CMD_KGDB) 578 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 579 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 580 #endif 581 582 /* 583 * Environment Configuration 584 */ 585 586 /* The mac addresses for all ethernet interface */ 587 #if defined(CONFIG_TSEC_ENET) 588 #define CONFIG_HAS_ETH0 589 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 590 #define CONFIG_HAS_ETH1 591 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 592 #define CONFIG_HAS_ETH2 593 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 594 #define CONFIG_HAS_ETH3 595 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 596 #endif 597 598 #define CONFIG_IPADDR 192.168.1.254 599 600 #define CONFIG_HOSTNAME unknown 601 #define CONFIG_ROOTPATH /opt/nfsroot 602 #define CONFIG_BOOTFILE uImage 603 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 604 605 #define CONFIG_SERVERIP 192.168.1.1 606 #define CONFIG_GATEWAYIP 192.168.1.1 607 #define CONFIG_NETMASK 255.255.255.0 608 609 /* default location for tftp and bootm */ 610 #define CONFIG_LOADADDR 1000000 611 612 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 613 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 614 615 #define CONFIG_BAUDRATE 115200 616 617 #define CONFIG_EXTRA_ENV_SETTINGS \ 618 "netdev=eth0\0" \ 619 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 620 "tftpflash=tftpboot $loadaddr $uboot; " \ 621 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 622 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 623 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 624 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 625 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 626 "consoledev=ttyS0\0" \ 627 "ramdiskaddr=2000000\0" \ 628 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 629 "fdtaddr=c00000\0" \ 630 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 631 "bdev=sda3\0" 632 633 #define CONFIG_HDBOOT \ 634 "setenv bootargs root=/dev/$bdev rw " \ 635 "console=$consoledev,$baudrate $othbootargs;" \ 636 "tftp $loadaddr $bootfile;" \ 637 "tftp $fdtaddr $fdtfile;" \ 638 "bootm $loadaddr - $fdtaddr" 639 640 #define CONFIG_NFSBOOTCOMMAND \ 641 "setenv bootargs root=/dev/nfs rw " \ 642 "nfsroot=$serverip:$rootpath " \ 643 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 644 "console=$consoledev,$baudrate $othbootargs;" \ 645 "tftp $loadaddr $bootfile;" \ 646 "tftp $fdtaddr $fdtfile;" \ 647 "bootm $loadaddr - $fdtaddr" 648 649 #define CONFIG_RAMBOOTCOMMAND \ 650 "setenv bootargs root=/dev/ram rw " \ 651 "console=$consoledev,$baudrate $othbootargs;" \ 652 "tftp $ramdiskaddr $ramdiskfile;" \ 653 "tftp $loadaddr $bootfile;" \ 654 "tftp $fdtaddr $fdtfile;" \ 655 "bootm $loadaddr $ramdiskaddr $fdtaddr" 656 657 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 658 659 #endif /* __CONFIG_H */ 660