1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 #include "../board/freescale/common/ics307_clk.h" 17 18 #ifdef CONFIG_36BIT 19 #define CONFIG_PHYS_64BIT 1 20 #endif 21 22 #ifdef CONFIG_SDCARD 23 #define CONFIG_RAMBOOT_SDCARD 1 24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 26 #endif 27 28 #ifdef CONFIG_SPIFLASH 29 #define CONFIG_RAMBOOT_SPIFLASH 1 30 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 31 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 32 #endif 33 34 #ifndef CONFIG_SYS_TEXT_BASE 35 #define CONFIG_SYS_TEXT_BASE 0xeff40000 36 #endif 37 38 #ifndef CONFIG_RESET_VECTOR_ADDRESS 39 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 40 #endif 41 42 #ifndef CONFIG_SYS_MONITOR_BASE 43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 44 #endif 45 46 /* High Level Configuration Options */ 47 #define CONFIG_BOOKE 1 /* BOOKE */ 48 #define CONFIG_E500 1 /* BOOKE e500 family */ 49 #define CONFIG_MPC8536 1 50 #define CONFIG_MPC8536DS 1 51 52 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 53 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 54 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 55 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 56 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 57 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 58 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 59 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 60 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 61 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 62 63 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 64 65 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 66 #define CONFIG_ENV_OVERWRITE 67 68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 69 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 70 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 71 72 /* 73 * These can be toggled for performance analysis, otherwise use default. 74 */ 75 #define CONFIG_L2_CACHE /* toggle L2 cache */ 76 #define CONFIG_BTB /* toggle branch predition */ 77 78 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 79 80 #define CONFIG_ENABLE_36BIT_PHYS 1 81 82 #ifdef CONFIG_PHYS_64BIT 83 #define CONFIG_ADDR_MAP 1 84 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 85 #endif 86 87 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 88 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 89 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 90 91 /* 92 * Config the L2 Cache as L2 SRAM 93 */ 94 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 95 #ifdef CONFIG_PHYS_64BIT 96 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 97 #else 98 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 99 #endif 100 #define CONFIG_SYS_L2_SIZE (512 << 10) 101 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 102 103 #define CONFIG_SYS_CCSRBAR 0xffe00000 104 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 105 106 #if defined(CONFIG_NAND_SPL) 107 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 108 #endif 109 110 /* DDR Setup */ 111 #define CONFIG_VERY_BIG_RAM 112 #define CONFIG_SYS_FSL_DDR2 113 #undef CONFIG_FSL_DDR_INTERACTIVE 114 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 115 #define CONFIG_DDR_SPD 116 117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 118 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 119 120 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 122 123 #define CONFIG_NUM_DDR_CONTROLLERS 1 124 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 125 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 126 127 /* I2C addresses of SPD EEPROMs */ 128 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 129 #define CONFIG_SYS_SPD_BUS_NUM 1 130 131 /* These are used when DDR doesn't use SPD. */ 132 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 133 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 134 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 135 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 136 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 137 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 138 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 139 #define CONFIG_SYS_DDR_MODE_1 0x00480432 140 #define CONFIG_SYS_DDR_MODE_2 0x00000000 141 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 142 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 143 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 144 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 145 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 146 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 147 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 148 149 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 150 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 151 #define CONFIG_SYS_DDR_SBE 0x00010000 152 153 /* Make sure required options are set */ 154 #ifndef CONFIG_SPD_EEPROM 155 #error ("CONFIG_SPD_EEPROM is required") 156 #endif 157 158 #undef CONFIG_CLOCKS_IN_MHZ 159 160 161 /* 162 * Memory map -- xxx -this is wrong, needs updating 163 * 164 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 165 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 166 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 167 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 168 * 169 * Localbus cacheable (TBD) 170 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 171 * 172 * Localbus non-cacheable 173 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 174 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 175 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 176 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 177 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 178 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 179 */ 180 181 /* 182 * Local Bus Definitions 183 */ 184 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 185 #ifdef CONFIG_PHYS_64BIT 186 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 187 #else 188 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 189 #endif 190 191 #define CONFIG_FLASH_BR_PRELIM \ 192 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 193 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 194 195 #define CONFIG_SYS_BR1_PRELIM \ 196 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 197 | BR_PS_16 | BR_V) 198 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 199 200 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 201 CONFIG_SYS_FLASH_BASE_PHYS } 202 #define CONFIG_SYS_FLASH_QUIET_TEST 203 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 204 205 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 207 #undef CONFIG_SYS_FLASH_CHECKSUM 208 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 209 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 210 211 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 212 #define CONFIG_SYS_RAMBOOT 213 #define CONFIG_SYS_EXTRA_ENV_RELOC 214 #else 215 #undef CONFIG_SYS_RAMBOOT 216 #endif 217 218 #define CONFIG_FLASH_CFI_DRIVER 219 #define CONFIG_SYS_FLASH_CFI 220 #define CONFIG_SYS_FLASH_EMPTY_INFO 221 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 222 223 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 224 225 #define CONFIG_HWCONFIG /* enable hwconfig */ 226 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 227 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 228 #ifdef CONFIG_PHYS_64BIT 229 #define PIXIS_BASE_PHYS 0xfffdf0000ull 230 #else 231 #define PIXIS_BASE_PHYS PIXIS_BASE 232 #endif 233 234 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 235 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 236 237 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 238 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 239 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 240 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 241 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 242 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 243 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 244 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 245 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 246 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 247 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 248 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 249 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 250 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 251 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 252 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 253 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 254 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 255 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 256 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 257 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 258 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 259 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 260 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 261 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 262 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 263 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 264 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 265 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 266 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 267 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 268 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 269 #define PIXIS_LED 0x25 /* LED Register */ 270 271 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 272 273 /* old pixis referenced names */ 274 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 275 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 276 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 277 278 #define CONFIG_SYS_INIT_RAM_LOCK 1 279 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 280 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 281 282 #define CONFIG_SYS_GBL_DATA_OFFSET \ 283 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 284 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 285 286 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 287 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 288 289 #ifndef CONFIG_NAND_SPL 290 #define CONFIG_SYS_NAND_BASE 0xffa00000 291 #ifdef CONFIG_PHYS_64BIT 292 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 293 #else 294 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 295 #endif 296 #else 297 #define CONFIG_SYS_NAND_BASE 0xfff00000 298 #ifdef CONFIG_PHYS_64BIT 299 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 300 #else 301 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 302 #endif 303 #endif 304 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 305 CONFIG_SYS_NAND_BASE + 0x40000, \ 306 CONFIG_SYS_NAND_BASE + 0x80000, \ 307 CONFIG_SYS_NAND_BASE + 0xC0000} 308 #define CONFIG_SYS_MAX_NAND_DEVICE 4 309 #define CONFIG_CMD_NAND 1 310 #define CONFIG_NAND_FSL_ELBC 1 311 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 312 313 /* NAND boot: 4K NAND loader config */ 314 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 315 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 316 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 317 #define CONFIG_SYS_NAND_U_BOOT_START \ 318 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 319 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 320 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 321 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 322 323 /* NAND flash config */ 324 #define CONFIG_SYS_NAND_BR_PRELIM \ 325 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 326 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 327 | BR_PS_8 /* Port Size = 8 bit */ \ 328 | BR_MS_FCM /* MSEL = FCM */ \ 329 | BR_V) /* valid */ 330 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 331 | OR_FCM_PGS /* Large Page*/ \ 332 | OR_FCM_CSCT \ 333 | OR_FCM_CST \ 334 | OR_FCM_CHT \ 335 | OR_FCM_SCY_1 \ 336 | OR_FCM_TRLX \ 337 | OR_FCM_EHTR) 338 339 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 340 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 341 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 342 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 343 344 #define CONFIG_SYS_BR4_PRELIM \ 345 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 346 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 347 | BR_PS_8 /* Port Size = 8 bit */ \ 348 | BR_MS_FCM /* MSEL = FCM */ \ 349 | BR_V) /* valid */ 350 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 351 #define CONFIG_SYS_BR5_PRELIM \ 352 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 353 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 354 | BR_PS_8 /* Port Size = 8 bit */ \ 355 | BR_MS_FCM /* MSEL = FCM */ \ 356 | BR_V) /* valid */ 357 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 358 359 #define CONFIG_SYS_BR6_PRELIM \ 360 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 361 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 362 | BR_PS_8 /* Port Size = 8 bit */ \ 363 | BR_MS_FCM /* MSEL = FCM */ \ 364 | BR_V) /* valid */ 365 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 366 367 /* Serial Port - controlled on board with jumper J8 368 * open - index 2 369 * shorted - index 1 370 */ 371 #define CONFIG_CONS_INDEX 1 372 #define CONFIG_SYS_NS16550 373 #define CONFIG_SYS_NS16550_SERIAL 374 #define CONFIG_SYS_NS16550_REG_SIZE 1 375 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 376 #ifdef CONFIG_NAND_SPL 377 #define CONFIG_NS16550_MIN_FUNCTIONS 378 #endif 379 380 #define CONFIG_SYS_BAUDRATE_TABLE \ 381 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 382 383 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 384 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 385 386 /* Use the HUSH parser */ 387 #define CONFIG_SYS_HUSH_PARSER 388 389 /* 390 * Pass open firmware flat tree 391 */ 392 #define CONFIG_OF_LIBFDT 1 393 #define CONFIG_OF_BOARD_SETUP 1 394 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 395 396 /* 397 * I2C 398 */ 399 #define CONFIG_SYS_I2C 400 #define CONFIG_SYS_I2C_FSL 401 #define CONFIG_SYS_FSL_I2C_SPEED 400000 402 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 403 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 404 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 405 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 406 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 407 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 408 409 /* 410 * I2C2 EEPROM 411 */ 412 #define CONFIG_ID_EEPROM 413 #ifdef CONFIG_ID_EEPROM 414 #define CONFIG_SYS_I2C_EEPROM_NXID 415 #endif 416 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 417 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 418 #define CONFIG_SYS_EEPROM_BUS_NUM 1 419 420 /* 421 * eSPI - Enhanced SPI 422 */ 423 #define CONFIG_HARD_SPI 424 #define CONFIG_FSL_ESPI 425 426 #if defined(CONFIG_SPI_FLASH) 427 #define CONFIG_SPI_FLASH_SPANSION 428 #define CONFIG_CMD_SF 429 #define CONFIG_SF_DEFAULT_SPEED 10000000 430 #define CONFIG_SF_DEFAULT_MODE 0 431 #endif 432 433 /* 434 * General PCI 435 * Memory space is mapped 1-1, but I/O space must start from 0. 436 */ 437 438 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 439 #ifdef CONFIG_PHYS_64BIT 440 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 441 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 442 #else 443 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 444 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 445 #endif 446 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 447 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 448 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 449 #ifdef CONFIG_PHYS_64BIT 450 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 451 #else 452 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 453 #endif 454 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 455 456 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 457 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 458 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 461 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 462 #else 463 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 464 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 465 #endif 466 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 467 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 468 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 469 #ifdef CONFIG_PHYS_64BIT 470 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 471 #else 472 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 473 #endif 474 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 475 476 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 477 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 478 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 479 #ifdef CONFIG_PHYS_64BIT 480 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 481 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 482 #else 483 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 484 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 485 #endif 486 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 487 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 488 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 491 #else 492 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 493 #endif 494 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 495 496 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 497 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 498 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 499 #ifdef CONFIG_PHYS_64BIT 500 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 501 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 502 #else 503 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 504 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 505 #endif 506 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 507 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 508 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 509 #ifdef CONFIG_PHYS_64BIT 510 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 511 #else 512 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 513 #endif 514 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 515 516 #if defined(CONFIG_PCI) 517 518 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 519 520 /*PCIE video card used*/ 521 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 522 523 /*PCI video card used*/ 524 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 525 526 /* video */ 527 #define CONFIG_VIDEO 528 529 #if defined(CONFIG_VIDEO) 530 #define CONFIG_BIOSEMU 531 #define CONFIG_CFB_CONSOLE 532 #define CONFIG_VIDEO_SW_CURSOR 533 #define CONFIG_VGA_AS_SINGLE_DEVICE 534 #define CONFIG_ATI_RADEON_FB 535 #define CONFIG_VIDEO_LOGO 536 /*#define CONFIG_CONSOLE_CURSOR*/ 537 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 538 #endif 539 540 #undef CONFIG_EEPRO100 541 #undef CONFIG_TULIP 542 #undef CONFIG_RTL8139 543 544 #ifndef CONFIG_PCI_PNP 545 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 546 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 547 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 548 #endif 549 550 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 551 552 #endif /* CONFIG_PCI */ 553 554 /* SATA */ 555 #define CONFIG_LIBATA 556 #define CONFIG_FSL_SATA 557 558 #define CONFIG_SYS_SATA_MAX_DEVICE 2 559 #define CONFIG_SATA1 560 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 561 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 562 #define CONFIG_SATA2 563 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 564 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 565 566 #ifdef CONFIG_FSL_SATA 567 #define CONFIG_LBA48 568 #define CONFIG_CMD_SATA 569 #define CONFIG_DOS_PARTITION 570 #define CONFIG_CMD_EXT2 571 #endif 572 573 #if defined(CONFIG_TSEC_ENET) 574 575 #define CONFIG_MII 1 /* MII PHY management */ 576 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 577 #define CONFIG_TSEC1 1 578 #define CONFIG_TSEC1_NAME "eTSEC1" 579 #define CONFIG_TSEC3 1 580 #define CONFIG_TSEC3_NAME "eTSEC3" 581 582 #define CONFIG_FSL_SGMII_RISER 1 583 #define SGMII_RISER_PHY_OFFSET 0x1c 584 585 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 586 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 587 588 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 589 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 590 591 #define TSEC1_PHYIDX 0 592 #define TSEC3_PHYIDX 0 593 594 #define CONFIG_ETHPRIME "eTSEC1" 595 596 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 597 598 #endif /* CONFIG_TSEC_ENET */ 599 600 /* 601 * Environment 602 */ 603 604 #if defined(CONFIG_SYS_RAMBOOT) 605 #if defined(CONFIG_RAMBOOT_SPIFLASH) 606 #define CONFIG_ENV_IS_IN_SPI_FLASH 607 #define CONFIG_ENV_SPI_BUS 0 608 #define CONFIG_ENV_SPI_CS 0 609 #define CONFIG_ENV_SPI_MAX_HZ 10000000 610 #define CONFIG_ENV_SPI_MODE 0 611 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 612 #define CONFIG_ENV_OFFSET 0xF0000 613 #define CONFIG_ENV_SECT_SIZE 0x10000 614 #elif defined(CONFIG_RAMBOOT_SDCARD) 615 #define CONFIG_ENV_IS_IN_MMC 616 #define CONFIG_FSL_FIXED_MMC_LOCATION 617 #define CONFIG_ENV_SIZE 0x2000 618 #define CONFIG_SYS_MMC_ENV_DEV 0 619 #else 620 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 621 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 622 #define CONFIG_ENV_SIZE 0x2000 623 #endif 624 #else 625 #define CONFIG_ENV_IS_IN_FLASH 1 626 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 627 #define CONFIG_ENV_SIZE 0x2000 628 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 629 #endif 630 631 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 632 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 633 634 /* 635 * Command line configuration. 636 */ 637 #define CONFIG_CMD_IRQ 638 #define CONFIG_CMD_PING 639 #define CONFIG_CMD_I2C 640 #define CONFIG_CMD_MII 641 #define CONFIG_CMD_ELF 642 #define CONFIG_CMD_IRQ 643 #define CONFIG_CMD_REGINFO 644 645 #if defined(CONFIG_PCI) 646 #define CONFIG_CMD_PCI 647 #endif 648 649 #undef CONFIG_WATCHDOG /* watchdog disabled */ 650 651 #define CONFIG_MMC 1 652 653 #ifdef CONFIG_MMC 654 #define CONFIG_FSL_ESDHC 655 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 656 #define CONFIG_CMD_MMC 657 #define CONFIG_GENERIC_MMC 658 #endif 659 660 /* 661 * USB 662 */ 663 #define CONFIG_HAS_FSL_MPH_USB 664 #ifdef CONFIG_HAS_FSL_MPH_USB 665 #define CONFIG_USB_EHCI 666 667 #ifdef CONFIG_USB_EHCI 668 #define CONFIG_CMD_USB 669 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 670 #define CONFIG_USB_EHCI_FSL 671 #define CONFIG_USB_STORAGE 672 #endif 673 #endif 674 675 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 676 #define CONFIG_CMD_EXT2 677 #define CONFIG_CMD_FAT 678 #define CONFIG_DOS_PARTITION 679 #endif 680 681 /* 682 * Miscellaneous configurable options 683 */ 684 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 685 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 686 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 687 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 688 #if defined(CONFIG_CMD_KGDB) 689 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 690 #else 691 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 692 #endif 693 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 694 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 695 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 696 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 697 698 /* 699 * For booting Linux, the board info and command line data 700 * have to be in the first 64 MB of memory, since this is 701 * the maximum mapped by the Linux kernel during initialization. 702 */ 703 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 704 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 705 706 #if defined(CONFIG_CMD_KGDB) 707 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 708 #endif 709 710 /* 711 * Environment Configuration 712 */ 713 714 /* The mac addresses for all ethernet interface */ 715 #if defined(CONFIG_TSEC_ENET) 716 #define CONFIG_HAS_ETH0 717 #define CONFIG_HAS_ETH1 718 #define CONFIG_HAS_ETH2 719 #define CONFIG_HAS_ETH3 720 #endif 721 722 #define CONFIG_IPADDR 192.168.1.254 723 724 #define CONFIG_HOSTNAME unknown 725 #define CONFIG_ROOTPATH "/opt/nfsroot" 726 #define CONFIG_BOOTFILE "uImage" 727 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 728 729 #define CONFIG_SERVERIP 192.168.1.1 730 #define CONFIG_GATEWAYIP 192.168.1.1 731 #define CONFIG_NETMASK 255.255.255.0 732 733 /* default location for tftp and bootm */ 734 #define CONFIG_LOADADDR 1000000 735 736 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 737 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 738 739 #define CONFIG_BAUDRATE 115200 740 741 #define CONFIG_EXTRA_ENV_SETTINGS \ 742 "netdev=eth0\0" \ 743 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 744 "tftpflash=tftpboot $loadaddr $uboot; " \ 745 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 746 " +$filesize; " \ 747 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 748 " +$filesize; " \ 749 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 750 " $filesize; " \ 751 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 752 " +$filesize; " \ 753 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 754 " $filesize\0" \ 755 "consoledev=ttyS0\0" \ 756 "ramdiskaddr=2000000\0" \ 757 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 758 "fdtaddr=c00000\0" \ 759 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 760 "bdev=sda3\0" \ 761 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 762 763 #define CONFIG_HDBOOT \ 764 "setenv bootargs root=/dev/$bdev rw " \ 765 "console=$consoledev,$baudrate $othbootargs;" \ 766 "tftp $loadaddr $bootfile;" \ 767 "tftp $fdtaddr $fdtfile;" \ 768 "bootm $loadaddr - $fdtaddr" 769 770 #define CONFIG_NFSBOOTCOMMAND \ 771 "setenv bootargs root=/dev/nfs rw " \ 772 "nfsroot=$serverip:$rootpath " \ 773 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 774 "console=$consoledev,$baudrate $othbootargs;" \ 775 "tftp $loadaddr $bootfile;" \ 776 "tftp $fdtaddr $fdtfile;" \ 777 "bootm $loadaddr - $fdtaddr" 778 779 #define CONFIG_RAMBOOTCOMMAND \ 780 "setenv bootargs root=/dev/ram rw " \ 781 "console=$consoledev,$baudrate $othbootargs;" \ 782 "tftp $ramdiskaddr $ramdiskfile;" \ 783 "tftp $loadaddr $bootfile;" \ 784 "tftp $fdtaddr $fdtfile;" \ 785 "bootm $loadaddr $ramdiskaddr $fdtaddr" 786 787 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 788 789 #endif /* __CONFIG_H */ 790