1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8536 1 35 #define CONFIG_MPC8536DS 1 36 37 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 38 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 39 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 40 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 41 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 44 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 45 46 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 47 48 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 49 #define CONFIG_ENV_OVERWRITE 50 51 /* 52 * When initializing flash, if we cannot find the manufacturer ID, 53 * assume this is the AMD flash associated with the CDS board. 54 * This allows booting from a promjet. 55 */ 56 #define CONFIG_ASSUME_AMD_FLASH 57 58 #ifndef __ASSEMBLY__ 59 extern unsigned long get_board_sys_clk(unsigned long dummy); 60 extern unsigned long get_board_ddr_clk(unsigned long dummy); 61 #endif 62 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 63 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) 64 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 65 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 66 from ICS307 instead of switches */ 67 68 /* 69 * These can be toggled for performance analysis, otherwise use default. 70 */ 71 #define CONFIG_L2_CACHE /* toggle L2 cache */ 72 #define CONFIG_BTB /* toggle branch predition */ 73 74 #define CONFIG_ENABLE_36BIT_PHYS 1 75 76 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 77 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 78 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 79 80 /* 81 * Base addresses -- Note these are effective addresses where the 82 * actual resources get mapped (not physical addresses) 83 */ 84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 85 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 86 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 87 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 88 89 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 90 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 91 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 92 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) 93 94 /* DDR Setup */ 95 #define CONFIG_FSL_DDR2 96 #undef CONFIG_FSL_DDR_INTERACTIVE 97 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 98 #define CONFIG_DDR_SPD 99 #undef CONFIG_DDR_DLL 100 101 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 102 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 103 104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 110 111 /* I2C addresses of SPD EEPROMs */ 112 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 113 #define CONFIG_SYS_SPD_BUS_NUM 1 114 115 /* These are used when DDR doesn't use SPD. */ 116 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 118 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 121 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 122 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 123 #define CONFIG_SYS_DDR_MODE_1 0x00480432 124 #define CONFIG_SYS_DDR_MODE_2 0x00000000 125 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 126 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 127 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 129 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 131 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 132 133 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 134 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 135 #define CONFIG_SYS_DDR_SBE 0x00010000 136 137 /* Make sure required options are set */ 138 #ifndef CONFIG_SPD_EEPROM 139 #error ("CONFIG_SPD_EEPROM is required") 140 #endif 141 142 #undef CONFIG_CLOCKS_IN_MHZ 143 144 145 /* 146 * Memory map -- xxx -this is wrong, needs updating 147 * 148 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 149 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 150 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 151 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 152 * 153 * Localbus cacheable (TBD) 154 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 155 * 156 * Localbus non-cacheable 157 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 158 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 159 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 160 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 161 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 162 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 163 */ 164 165 /* 166 * Local Bus Definitions 167 */ 168 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 169 170 #define CONFIG_SYS_BR0_PRELIM 0xe8001001 171 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 172 173 #define CONFIG_SYS_BR1_PRELIM 0xe0001001 174 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 175 176 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} 177 #define CONFIG_SYS_FLASH_QUIET_TEST 178 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 179 180 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 181 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 182 #undef CONFIG_SYS_FLASH_CHECKSUM 183 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 184 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 185 186 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 187 188 #define CONFIG_FLASH_CFI_DRIVER 189 #define CONFIG_SYS_FLASH_CFI 190 #define CONFIG_SYS_FLASH_EMPTY_INFO 191 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 192 193 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 194 195 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 196 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 197 198 #define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ 199 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 200 201 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 202 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 203 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 204 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 205 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 206 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 207 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 208 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 209 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 210 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 211 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 212 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 213 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 214 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 215 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 216 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 217 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 218 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 219 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 220 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 221 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 222 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 223 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 224 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 225 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 226 #define PIXIS_LED 0x25 /* LED Register */ 227 228 /* old pixis referenced names */ 229 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 230 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 231 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 232 233 #define CONFIG_SYS_INIT_RAM_LOCK 1 234 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 235 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 236 237 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 238 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 239 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 240 241 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 242 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 243 244 #define CONFIG_SYS_NAND_BASE 0xffa00000 245 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 246 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 247 CONFIG_SYS_NAND_BASE + 0x40000, \ 248 CONFIG_SYS_NAND_BASE + 0x80000, \ 249 CONFIG_SYS_NAND_BASE + 0xC0000} 250 #define CONFIG_SYS_MAX_NAND_DEVICE 4 251 #define NAND_MAX_CHIPS 1 252 #define CONFIG_MTD_NAND_VERIFY_WRITE 253 #define CONFIG_CMD_NAND 1 254 #define CONFIG_NAND_FSL_ELBC 1 255 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 256 257 /* NAND flash config */ 258 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 259 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 260 | BR_PS_8 /* Port Size = 8 bit */ \ 261 | BR_MS_FCM /* MSEL = FCM */ \ 262 | BR_V) /* valid */ 263 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 264 | OR_FCM_PGS /* Large Page*/ \ 265 | OR_FCM_CSCT \ 266 | OR_FCM_CST \ 267 | OR_FCM_CHT \ 268 | OR_FCM_SCY_1 \ 269 | OR_FCM_TRLX \ 270 | OR_FCM_EHTR) 271 272 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 273 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 274 275 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ 276 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 277 | BR_PS_8 /* Port Size = 8 bit */ \ 278 | BR_MS_FCM /* MSEL = FCM */ \ 279 | BR_V) /* valid */ 280 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 281 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 282 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 283 | BR_PS_8 /* Port Size = 8 bit */ \ 284 | BR_MS_FCM /* MSEL = FCM */ \ 285 | BR_V) /* valid */ 286 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 287 288 #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ 289 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 290 | BR_PS_8 /* Port Size = 8 bit */ \ 291 | BR_MS_FCM /* MSEL = FCM */ \ 292 | BR_V) /* valid */ 293 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 294 295 /* Serial Port - controlled on board with jumper J8 296 * open - index 2 297 * shorted - index 1 298 */ 299 #define CONFIG_CONS_INDEX 1 300 #undef CONFIG_SERIAL_SOFTWARE_FIFO 301 #define CONFIG_SYS_NS16550 302 #define CONFIG_SYS_NS16550_SERIAL 303 #define CONFIG_SYS_NS16550_REG_SIZE 1 304 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 305 306 #define CONFIG_SYS_BAUDRATE_TABLE \ 307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 308 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 311 312 /* Use the HUSH parser */ 313 #define CONFIG_SYS_HUSH_PARSER 314 #ifdef CONFIG_SYS_HUSH_PARSER 315 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 316 #endif 317 318 /* 319 * Pass open firmware flat tree 320 */ 321 #define CONFIG_OF_LIBFDT 1 322 #define CONFIG_OF_BOARD_SETUP 1 323 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 324 325 #define CONFIG_SYS_64BIT_STRTOUL 1 326 #define CONFIG_SYS_64BIT_VSPRINTF 1 327 328 329 /* 330 * I2C 331 */ 332 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 333 #define CONFIG_HARD_I2C /* I2C with hardware support */ 334 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 335 #define CONFIG_I2C_MULTI_BUS 336 #define CONFIG_I2C_CMD_TREE 337 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 338 #define CONFIG_SYS_I2C_SLAVE 0x7F 339 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 340 #define CONFIG_SYS_I2C_OFFSET 0x3000 341 #define CONFIG_SYS_I2C2_OFFSET 0x3100 342 343 /* 344 * I2C2 EEPROM 345 */ 346 #define CONFIG_ID_EEPROM 347 #ifdef CONFIG_ID_EEPROM 348 #define CONFIG_SYS_I2C_EEPROM_NXID 349 #endif 350 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 351 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 352 #define CONFIG_SYS_EEPROM_BUS_NUM 1 353 354 /* 355 * General PCI 356 * Memory space is mapped 1-1, but I/O space must start from 0. 357 */ 358 359 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 360 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 361 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 362 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 363 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 364 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 365 366 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 367 #define CONFIG_SYS_PCIE1_MEM_BASE 0x90000000 368 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE 369 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 370 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 371 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 372 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 373 374 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 375 #define CONFIG_SYS_PCIE2_MEM_BASE 0x98000000 376 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE 377 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 378 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 379 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 380 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 381 382 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 383 #define CONFIG_SYS_PCIE3_MEM_BASE 0xa0000000 384 #define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE 385 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 386 #define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 387 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 388 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 389 390 #if defined(CONFIG_PCI) 391 392 #define CONFIG_NET_MULTI 393 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 394 395 /*PCIE video card used*/ 396 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_PHYS 397 398 /*PCI video card used*/ 399 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/ 400 401 /* video */ 402 #define CONFIG_VIDEO 403 404 #if defined(CONFIG_VIDEO) 405 #define CONFIG_BIOSEMU 406 #define CONFIG_CFB_CONSOLE 407 #define CONFIG_VIDEO_SW_CURSOR 408 #define CONFIG_VGA_AS_SINGLE_DEVICE 409 #define CONFIG_ATI_RADEON_FB 410 #define CONFIG_VIDEO_LOGO 411 /*#define CONFIG_CONSOLE_CURSOR*/ 412 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_PHYS 413 #endif 414 415 #undef CONFIG_EEPRO100 416 #undef CONFIG_TULIP 417 #undef CONFIG_RTL8139 418 419 #ifdef CONFIG_RTL8139 420 /* This macro is used by RTL8139 but not defined in PPC architecture */ 421 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 422 #define _IO_BASE 0x00000000 423 #endif 424 425 #ifndef CONFIG_PCI_PNP 426 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 427 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE 428 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 429 #endif 430 431 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 432 433 #endif /* CONFIG_PCI */ 434 435 /* SATA */ 436 #define CONFIG_LIBATA 437 #define CONFIG_FSL_SATA 438 439 #define CONFIG_SYS_SATA_MAX_DEVICE 2 440 #define CONFIG_SATA1 441 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 442 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 443 #define CONFIG_SATA2 444 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 445 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 446 447 #ifdef CONFIG_FSL_SATA 448 #define CONFIG_LBA48 449 #define CONFIG_CMD_SATA 450 #define CONFIG_DOS_PARTITION 451 #define CONFIG_CMD_EXT2 452 #endif 453 454 #if defined(CONFIG_TSEC_ENET) 455 456 #ifndef CONFIG_NET_MULTI 457 #define CONFIG_NET_MULTI 1 458 #endif 459 460 #define CONFIG_MII 1 /* MII PHY management */ 461 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 462 #define CONFIG_TSEC1 1 463 #define CONFIG_TSEC1_NAME "eTSEC1" 464 #define CONFIG_TSEC3 1 465 #define CONFIG_TSEC3_NAME "eTSEC3" 466 467 #define CONFIG_FSL_SGMII_RISER 1 468 #define SGMII_RISER_PHY_OFFSET 0x1c 469 470 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 471 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 472 473 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 474 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 475 476 #define TSEC1_PHYIDX 0 477 #define TSEC3_PHYIDX 0 478 479 #define CONFIG_ETHPRIME "eTSEC1" 480 481 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 482 483 #endif /* CONFIG_TSEC_ENET */ 484 485 /* 486 * Environment 487 */ 488 #define CONFIG_ENV_IS_IN_FLASH 1 489 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 490 #define CONFIG_ENV_ADDR 0xfff80000 491 #else 492 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 493 #endif 494 #define CONFIG_ENV_SIZE 0x2000 495 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 496 497 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 498 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 499 500 /* 501 * Command line configuration. 502 */ 503 #include <config_cmd_default.h> 504 505 #define CONFIG_CMD_IRQ 506 #define CONFIG_CMD_PING 507 #define CONFIG_CMD_I2C 508 #define CONFIG_CMD_MII 509 #define CONFIG_CMD_ELF 510 #define CONFIG_CMD_IRQ 511 #define CONFIG_CMD_SETEXPR 512 513 #if defined(CONFIG_PCI) 514 #define CONFIG_CMD_PCI 515 #define CONFIG_CMD_BEDBUG 516 #define CONFIG_CMD_NET 517 #endif 518 519 #undef CONFIG_WATCHDOG /* watchdog disabled */ 520 521 /* 522 * Miscellaneous configurable options 523 */ 524 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 525 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 526 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 527 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 528 #if defined(CONFIG_CMD_KGDB) 529 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 530 #else 531 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 532 #endif 533 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 534 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 535 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 536 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 537 538 /* 539 * For booting Linux, the board info and command line data 540 * have to be in the first 8 MB of memory, since this is 541 * the maximum mapped by the Linux kernel during initialization. 542 */ 543 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 544 545 /* 546 * Internal Definitions 547 * 548 * Boot Flags 549 */ 550 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 551 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 552 553 #if defined(CONFIG_CMD_KGDB) 554 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 555 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 556 #endif 557 558 /* 559 * Environment Configuration 560 */ 561 562 /* The mac addresses for all ethernet interface */ 563 #if defined(CONFIG_TSEC_ENET) 564 #define CONFIG_HAS_ETH0 565 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 566 #define CONFIG_HAS_ETH1 567 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 568 #define CONFIG_HAS_ETH2 569 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 570 #define CONFIG_HAS_ETH3 571 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 572 #endif 573 574 #define CONFIG_IPADDR 192.168.1.254 575 576 #define CONFIG_HOSTNAME unknown 577 #define CONFIG_ROOTPATH /opt/nfsroot 578 #define CONFIG_BOOTFILE uImage 579 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 580 581 #define CONFIG_SERVERIP 192.168.1.1 582 #define CONFIG_GATEWAYIP 192.168.1.1 583 #define CONFIG_NETMASK 255.255.255.0 584 585 /* default location for tftp and bootm */ 586 #define CONFIG_LOADADDR 1000000 587 588 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 589 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 590 591 #define CONFIG_BAUDRATE 115200 592 593 #define CONFIG_EXTRA_ENV_SETTINGS \ 594 "netdev=eth0\0" \ 595 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 596 "tftpflash=tftpboot $loadaddr $uboot; " \ 597 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 598 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 599 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 600 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 601 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 602 "consoledev=ttyS0\0" \ 603 "ramdiskaddr=2000000\0" \ 604 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 605 "fdtaddr=c00000\0" \ 606 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 607 "bdev=sda3\0" 608 609 #define CONFIG_HDBOOT \ 610 "setenv bootargs root=/dev/$bdev rw " \ 611 "console=$consoledev,$baudrate $othbootargs;" \ 612 "tftp $loadaddr $bootfile;" \ 613 "tftp $fdtaddr $fdtfile;" \ 614 "bootm $loadaddr - $fdtaddr" 615 616 #define CONFIG_NFSBOOTCOMMAND \ 617 "setenv bootargs root=/dev/nfs rw " \ 618 "nfsroot=$serverip:$rootpath " \ 619 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 620 "console=$consoledev,$baudrate $othbootargs;" \ 621 "tftp $loadaddr $bootfile;" \ 622 "tftp $fdtaddr $fdtfile;" \ 623 "bootm $loadaddr - $fdtaddr" 624 625 #define CONFIG_RAMBOOTCOMMAND \ 626 "setenv bootargs root=/dev/ram rw " \ 627 "console=$consoledev,$baudrate $othbootargs;" \ 628 "tftp $ramdiskaddr $ramdiskfile;" \ 629 "tftp $loadaddr $bootfile;" \ 630 "tftp $fdtaddr $fdtfile;" \ 631 "bootm $loadaddr $ramdiskaddr $fdtaddr" 632 633 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 634 635 #endif /* __CONFIG_H */ 636